Fabrication process for a semiconductor substrate

Details Fabrication process for a semiconductor substrate Fabrication process for a semiconductor substrate

1997-02-27

2001-09-25

Powell, William (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Liquid phase etching

C438S756000, C438S747000, C148S033200, C148S033300, C148S033500

Reexamination Certificate

active

06294478

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a fabrication process for a semiconductor substrate and, more particularly, to a process for fabricating a single-crystal semiconductor on a dielectric isolation or an insulator and a single-crystal compound semiconductor on Si substrate and further to a process for fabricating a semiconductor substrate suitable for electronic devices and integrated circuits made in a single-crystal semiconductor layer.
2. Related Background Art
Formation of a single-crystal Si semiconductor layer on an insulator is widely known as Si On Insulator (SOI) technology and much research has been focused thereon, because devices obtained utilizing the SOI technology have many advantages that cannot be achieved by the normal bulk Si substrates for fabrication of Si integrated circuits. Namely, use of SOI technology can enjoy the following advantages, for example:
1. Dielectric isolation is easy and high integration is possible.
2. Radiation resistance is high.
3. Stray capacitance is reduced and the operation speed can be enhanced.
4. The well process can be omitted.
5. Latch-up can be prevented.
6. Fully depleted field effect transistors can be fabricated by thin-film structure. These advantages are described in further detail, for example, in the reference [Special Issue: “Single-crystal silicon on non-single-crystal insulators”; edited by G. W. Cullen, Journal of Crystal Growth, volume 63, no 3, pp 429-590 (1983)].
In recent years, many reports have been presented on the SOI as a substrate focused on increase of speed and decrease of consumption power of MOSFET (IEEE SOI conference 1994). Since the SOI structure has an insulating layer below the device, use thereof can simplify the device isolation process as compared with forming the devices on a bulk Si wafer, which results in shortening the device process steps. Namely, in addition to the increase in performance, the total costs including the wafer cost and the process cost are expected to be lower than those of MOSFETs and ICs on bulk Si.
Among others, the fully depleted MOSFETs are expected to increase the speed and decrease the consumption power due to an improvement in driving force. The threshold voltage (Vth) of MOSFET is determined in general by an impurity concentration of the channel portion, and, in the case of the fully depleted (FD) MOSFETs using the SOI, the thickness of a depletion layer is also influenced by the film thickness of the SOI. Accordingly, evenness of the film thickness of SOI is highly desirable for fabricating large-scale integrated circuits with good yields.
On the other hand, the devices on a compound semiconductor have high performance that cannot be attained by Si, for example, high-speed operation, radiation of light, and so on. Presently, most of these devices are fabricated in a layer epitaxially grown on a compound semiconductor substrate of GaAs or the like. The compound semiconductor substrates, however, have problems such as high expensive, low mechanical strength, difficulty in fabricating a large-area wafer, etc.
Because of these problems, attempts have been made to hetero-epitaxially grow a compound semiconductor on the Si wafer, which is cheap, has high mechanical strength, and permits fabrication of a large-area wafer.
Returning to the SOI structure, research on formation of SOI substrates has been active since the 1970s. In the early stage, much research was focused on a method for hetero-epitaxially growing single-crystal Si on a sapphire substrate as an insulator (SOS: Silicon on Sapphire), a method for forming the SOI structure by dielectric isolation based on oxidation of porous Si (FIPOS: Full Isolation by Porous Oxidized Silicon), and an oxygen ion implantation method.
The FIPOS method is a method for forming an n-type Si layer in an island pattern on a surface of a p-type Si single-crystal substrate by proton implantation (Imai et al., J. Crystal Growth, vol 63, 547 (1983)) or by epitaxial growth and patterning, making only the p-type Si substrate porous from the surface, so as to surround Si islands by anodization in HF solution, and then dielectric-isolating the n-type Si islands by enhanced oxidation. This method has a problem in that degrees of freedom on device designing are limited, because the Si regions isolated are determined prior to the device processes.
The oxygen ion implantation method is called SIMOX, which was first reported by K. Izumi. Oxygen ions are first implanted in about 10
17
to 10
18
/cm
2
into Si wafer, and thereafter the wafer is annealed at a high temperature of approximately 1320° C. in an argon-oxygen atmosphere. As a result, the oxygen ions implanted around the depth corresponding to the projected range (Rp) of ion implantation are bound with Si to form an oxidized Si layer. At that point, a Si layer, amorphized by the oxygen ion implantation above the oxidized Si layer, is also recrystallized to form a single-crystal Si layer. Crystalline defects in the surface Si layer were as many as 10
5
/cm
2
before, but they were successfully decreased to below 10
2
/cm
2
by adjusting the amount of implantation of oxygen to approximately 4×10
17
/cm
2
. However, the film thicknesses of the surface Si layer and the buried, oxidized Si layer (BOX; Buried Oxide) were limited to specific values due to narrow ranges of implantation energy and implantation dose capable of maintaining the film quality of the oxidized Si layer, crystallinity of the surface Si layer, and so on. Sacrificial oxidation or epitaxial growth was necessary for obtaining the surface Si layer in a desired film thickness. In that case, there is a problem that evenness of film thickness is degraded, because degradation due to these processes is added on the distribution of film thickness.
It is also reported that malformed regions of oxidized Si called pipes exist in the BOX. One of causes thereof is conceivably contaminations such as dust upon implantation. In the portions including the pipes, degradation of device characteristics occurs due to leakage between the active layer and the support substrate.
Since the implantation dose in the ion implantation of SIMOX is larger than in the ion implantation used for the normal semiconductor processes as described previously, the implantation time is still long even after dedicated equipment has been developed. Since the ion implantation is carried out by raster scan of an ion beam of a predetermined electric current amount or by expanding the beam, an increase in the implantation time is anticipated with an increase in the area of wafer. In high-temperature annealing of a large-area wafer, it is pointed out that the problem of generation of slip or the like due to the temperature distribution within the wafer becomes more severe. Annealing at high temperatures, such as 1320° C., which are not used normally in the Si semiconductor processes, is indispensable for the SIMOX, and there is thus such a concern that the above problem becomes more significant, including development of equipment.
Aside from the conventional SOI forming methods described above, attention has recently focused on another method for bonding Si single-crystal substrate to another Si single-crystal substrate thermally oxidized, by annealing or with an adhesive, thereby forming the SOI structure. This method requires evenly thinning the active layer for the device. In other words, it is necessary to thin the Si single-crystal substrate even several hundred &mgr;m thick down to the order of &mgr;m or less. The following three types of methods are available for this thinning:
(1) thinning by polishing
(2) thinning by localized plasma etching
(3) thinning by selective etching.
It is difficult to achieve uniform thinning by the polishing method of (1). In particular, several ten % of dispersion appears in thinning on the sub-&mgr;m order, and evening of this dispersion is a big problem. The degree of difficulty increases with further increases in the diameter of a given wafer.
The above method

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