Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2002-05-22
2004-09-28
Nguyen, Thanh (Department: 2813)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S240000, C438S216000, C438S261000, C438S591000
Reexamination Certificate
active
06797525
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor devices, and more specifically to a fabrication process for a semiconductor device having a metal oxide dielectric material with a high dielectric constant.
2. Description of the Related Art
As the dimensions of the MOS transistor are scaled down, the thickness of its gate oxide, typically SiO
2
, decreases accordingly. Reducing the SiO
2
layer to an ultrathin thickness results in charge carrier leakage by tunneling conduction as the ultrathin SiO
2
gate oxide layer no longer functions as an effective insulator.
Tunneling conduction also causes a faster dissipation of stored charge resulting in, for example, shortened battery life in portable devices such as cellular telephones and laptop computers. Typically, the gate dielectric layer used in a MOS transistor is an SiO
2
layer which has a dielectric constant of 3.9. Alternative gate oxide materials possessing a higher dielectric constant than SiO
2
would allow one to achieve the same gate capacitance in a thicker (physical thickness) gate dielectric layer. A thicker gate dielectric layer possessing a higher dielectric constant would provide for reduced tunnel leakage, while resulting in the same or larger gate capacitance as an SiO
2
layer.
Typical high-K materials which have been proposed for use as a gate oxide are metal oxides such as e.g., HfO
2
, Al
2
O
3
, La
2
O
3
, Ta
2
O
5
, ZrO
2
, TiO
2
, and combinations of these metal oxides with SiO
2
(i.e., forming silicates) and Al
2
O
3
(i.e., forming aluminates). The term silicate as used herein is a metal in combination with SiO
2
or SiON forming a silicate or silicate oxynitride structure, or a nitrided silicate structure with the top portion of the silicate being converted to a nitride (for example, by plasma nitridation, thermal nitridation, or implantation by nitrogen atoms; using techniques known to those skilled in the art). The term aluminate, as used herein is a metal in combination with Al
2
O
3
or AlON forming an aluminate or aluminate oxynitride structure, or a nitrided aluminate structure with the top portion of the aluminate being converted to a nitride (for example, by plasma nitridation, thermal nitridation, or implantation by nitrogen atoms; using techniques known to those skilled in the art). These materials are used in lieu of or in conjunction with the SiO
2
layer.
However, current high-K dielectric gate layers result in devices that suffer from low carrier mobility and drive current. Mobility degradation results from coulombic scattering from charge centers in the gate dielectric, phonon scattering from the oxide, as well as from interfacial (Si/SiO
2
) roughness at an Si/SiO
2
interface beneath the high-K gate dielectric. Elimination of the excess charge centers (commonly referred to as “fixed charge”) and a more uniform Si/SiO
2
interface would minimize carrier mobility degradation, due to either coulombic scattering or scattering at the interface.
In addition, after formation of a high-K gate dielectric, thermal processing steps, such as annealing the high-K dielectric layer, are often carried out. Such processing steps can result in an undesirably thick SiO
2
interfacial layer due to reoxidation of the Si/SiO
2
(silicon/silicon dioxide) interface. Capacitance is inversely proportional to the thickness of the gate oxide layer. The presence of a significantly reoxidized thicker SiO
2
layer at the interface dramatically decreases the capacitance and transconductance of the device. The purpose in utilizing alternative gate oxide materials, such as high-K materials, is to largely replace the SiO
2
layer. Therefore, the presence of a significantly reoxidized thicker SiO
2
layer is undesirable.
Moreover, a high-K gate dielectric is typically formed under conditions that result in anomalies in the overall charge of the fabricated high-K gate dielectric. Growing high-K gate dielectrics naturally results in deviations from its ideal stoichiometric state since its formation occurs under conditions far from its thermodynamic equilibrium. For example, current methods of fabricating a high-K ZrO
2
gate dielectric result in formation of ZrO
2−x
rather than ZrO
2
. Under ideal conditions, a fabricated high-K ZrO
2−x
gate dielectric would possess perfect stoichiometry (x equals zero) and have a net charge of zero since Zr has a +4 charge and O has a charge of −2. Realistically however, a net charge of zero is not obtained utilizing present fabrication methods and techniques. This results in an excess fixed charge in the high-K gate dielectric that can act as both coulombic scattering centers and as charge trapping centers. A substantial high fixed charge has been observed in all metal oxides that are used as alternatives to SiO
2
gate dielectric materials. Typically, high-K gate dielectrics have a fixed charge greater than 10
12
/cm
2
; whereas, SiO
2
typically has a fixed charge of 10
10
/cm
2
.
Additional problems arise when utilizing a metal oxide in lieu of SiO
2
as the gate dielectric material. An ultrathin layer of SiO
2
is typically provided as an interfacial layer when using a metal oxide rather than SiO
2
as the gate dielectric material. The interfacial layer is desirable because it facilitates nucleation and growth of the high-K dielectric layer. The interfacial layer also provides a good electrical interface with the silicon and has a low interfacial state density. Conventional methods of forming a metal oxide layer directly onto a silicon layer can also result in the inherent formation of an interfacial SiO
2
layer.
One problem with the Si/SiO
2
interface is graphically depicted in
FIG. 1
, which illustrates the thermodynamic chemical equilibrium between SiO (silicon oxide) and SiO
2
(silicon dioxide) as a function of partial pressure of oxygen and temperature. Above and at line
10
is an illustration of parameter space where SiO
2
forms (i.e., SiO
2
is stable and will grow in the presence of oxygen). For instance, silicon reacts in the presence of oxygen forming SiO
2
. Whereas below line
10
, SiO
2
does not form (i.e., SiO
2
is unstable) and if present, decomposes into SiO. In this case, silicon reacts in the presence of oxygen forming SiO. SiO is a volatile compound and thus, its formation and presence decomposes the interface between the underlying silicon substrate and interfacial layer.
Current methodologies for annealing high-K dielectric gate layers use annealing environments which occur above line
10
in FIG.
1
. Annealing at conditions above line
10
results in significant reoxidation of the underlying SiO
2
layer which is undesirable as noted above. Current regimes also use annealing environments which do not restore or attempt to restore a high-K gate dielectric layer's stoichiometry and can even drive the high-K gate dielectric farther from its stoichiometric point.
As a result, alternate practices are desired for annealing a high-K gate dielectric layer to mitigate the noted problems. A high-K gate dielectric must form an extremely high-quality interface with silicon or SiO
2
and must also withstand conventional transistor processing conditions. Accordingly, a desire and need exists for a process that yields a minimal amount of SiO
2
formed by further reoxidation of the silicon during the annealing process and which creates a high-K gate dielectric that is closer to its stoichiometric point to reduce the excess fixed charge.
BRIEF SUMMARY OF THE INVENTION
The present invention addresses the noted problems above and provides a method of fabricating a semiconductor device such as a MOSFET (metal-oxide semiconductor field effect transistor) utilizing a metal oxide dielectric material possessing a dielectric constant greater than SiO
2
. Specifically, the invention provides a processing sequence for the post-deposition annealing of a high-K metal oxide dielectric layer to produce a metal oxide dielectric layer having a lower fixed charge (i.e., a high-K metal oxide
Green Martin L.
Wilk Glen D.
Agere Systems Inc.
Dickstein , Shapiro, Morin & Oshinsky, LLP
Nguyen Thanh
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