Fabrication process for a dielectric isolated complementary inte

Details Fabrication process for a dielectric isolated complementary inte Fabrication process for a dielectric isolated complementary inte

1984-10-11

1986-11-25

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29571, 29578, 29576B, 29580, 148 15, 148175, 148DIG85, 148DIG38, 148DIG135, 357 42, 357 50, 357 54, 357 55, 357 59, 156654, 156649, H01L 2176, H01L 21302, H01L 2138

Patent

active

046240470

ABSTRACT:
A method for fabricating isolated regions for a dielectric isolated complementary integrated circuit which avoids the difficulty of mask alignment and patterning on a deeply etched uneven surface of the substrate by aligning the patterns before etching and thereby forming p-type and n-type islands at the same time. A poly-silicon layer is grown on the surface of the substrate covering the islands and the substrate is removed from its back surface, leaving the islands embedded in the poly-silicon layer which becomes a new substrate.

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patent: 3412296 (1968-11-01), Grebene
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patent: 4393573 (1983-07-01), Kato et al.
patent: 4481707 (1984-11-01), Cunniff
Grove, "Physics and Technology of Semiconductor Devices", Fairchild Semiconductor, Palo Alto, Univ. of Cal., Berkeley, 1967, pp. 36-41.

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