Fabrication of w-polycide-to-poly capacitors with high linearity

Details Fabrication of w-polycide-to-poly capacitors with high linearity Fabrication of w-polycide-to-poly capacitors with high linearity

1993-07-28

1995-02-28

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 47, 437919, 437200, H01L 2170, H01L 2700

Patent

active

053936914

ABSTRACT:
A method of forming a polycide-to-polysilicon capacitor with a low voltage coefficient and high linearity is described. A a first layer of polysilicon, having a suitable doping concentration, is deposited on the surface of the substrate and the field oxide regions. A layer of silicide is deposited over the polysilicon layer. The layer of silicide and the layer of polysilicon on the field oxide region are patterned, to form a polycide bottom plate of the capacitor. The polycide bottom plate is annealed. Sidewalls are formed on the sides of the polycide bottom plate. The polycide bottom plate is ion implanted in a vertical to produce the low voltage coefficient and high linearity. An interpoly dielectric layer is formed and patterned on the surface of the polycide bottom plate to act as a dielectric for the polycide-to-polysilicon capacitor. The interpoly dielectric layer is densified. A second layer of polysilicon, having a suitable doping concentration, is deposited on the surface of the dielectric layer and on the surface of the substrate and the field oxide regions. The second layer of polysilicon is patterned to form the top plate of the capacitor.

REFERENCES:
patent: 4971924 (1988-12-01), Tigelaar et al.
patent: 5037772 (1991-08-01), McDonald
patent: 5130267 (1992-07-01), Kaya et al.
patent: 5173437 (1992-12-01), Chi
patent: 5218511 (1993-06-01), Nariani

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