Fabrication of vertical NPN and PNP bipolar transistors in monol

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357 44, 357 50, 357 51, 357 34, H01L 2712

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046654259

ABSTRACT:
Vertical PNP and the NPN transistors, each having a gain-bandwidth product greater than 1 GHz are formed in dielectrically isolated regions in a polysilicon substrate. The substrate may include additional dielectrically isolated regions for other devices such as thin oxide capacitors. On one surface of the substrate between the respective device regions a thick field insulator (oxide) layer is formed to minimize parasitics between interconnects and the substrate. Atop this thick field oxide one or more thin film resistors may be formed. Contacts and interconnect metallization for the bipolar devices, capacitors and thin film resistors are preferably made of silicon-doped-aluminum. In the course of manufacture of the PNP and NPN devices like conductivity type regions are formed simultaneously so as to control the parameters of each device. The relatively high f.sub.T of each device is achieved by reducing the time delays associated with the devices, through precise control of the parameters of impurity introduction (ion implantation and diffusion steps), so as to obtain narrow base widths (thereby reducing the base transit times), narrow and shallow emitters (for reduced emitter delay and base resistance), and shallow bases and a low resistivity substrate (for reduced device size (high integration density) and collector delay). To minimize the incidence of emitter leakage "pipes", which typically occur in shallow bipolar devices, controlled anneal and oxygen gettering steps are carried out and emitter sheet resistance is optimized. Preferably base contacts are formed by dual, narrow stripe diffusions on opposite sides of a narrow emitter stripe.

REFERENCES:
patent: 4299024 (1981-11-01), Piotrowski
patent: 4536784 (1985-08-01), Nagumo et al.
patent: 4546539 (1985-10-01), Beasom

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