Fabrication of transistor having elevated source-drain and...

Details Fabrication of transistor having elevated source-drain and... Fabrication of transistor having elevated source-drain and...

2000-12-13

2003-03-11

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S288000, C257S774000, C257S753000

Reexamination Certificate

active

06531781

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention pertains to transistor, and particular to method for forming transistor that has both elevated source-drain and metal silicide.
2. Description of the Prior Art
One trend of the semiconductor industry is to make semiconductor devices as small as possible. However, process technology or methods used in forming such devices impose limitations on how small a device can be made.
A typical semiconductor device and a primary building block in the semiconductor industry is the transistor, especially the metal oxide semiconductor field effect transistor (MOSFET). Referring to
FIG. 1
, a MOSFET is typically composed of gate conductor layer
120
, sidewall
116
and gate dielectric layer
115
which both are formed over substrate
110
, herein gate conductor layer
120
is usually composed of polysilicon and gate dielectric layer
115
is usually composed of oxide. Within substrate
110
are formed deep source-drain regions
150
(sometimes referred to as heavily doped source and drain regions) and source-drain extension regions
130
(sometimes referred to as lightly doped source-drain region). In general, doped regions are regions contain a higher concentration of P-type or N-type dopants than substrate
110
. Source-drain extension regions
130
generally have a lower concentration of dopants compared to deep source-drain regions
150
, although sometimes these regions can be doped at equivalent levels. Further, source-drain extension regions
130
have a thickness, which is smaller than thickness of deep source-drain regions
150
. Shallow source-drain extension regions
130
are important for reducing hot carrier injection (HCI), which often occurs in scaled down (e.g. sub-micron) devices, and for maintaining other device characteristics such as threshold voltage rolloff, punchthrough, and other short channel characteristics. Thicker deep source-drain regions
150
are generally important for lowering device resistivity, for maxing device current and for forming contact.
In reducing the size of MOSFET devices, much of the focus has been on reducing the length of gate conductor
120
. As the length is reduced, however, the device size must also be reduced in the vertical direction. That is to say that thickness of source-drain extension regions
130
also must be reduced. However, formation of shallow source-drain extension regions
130
requires precise control of dopant distribution on a fine scale. Unfortunately, while technology will allow other portions of MOSFET devices to be scaled smaller, e.g. gates scaled in sub-micron lengths, limitations in forming finely scaled source-drain extension regions
130
have prevented semi-conductor devices from reaching their smallest dimensions. These limitations often arise as a result of heat steps, including annealing process for repairing and achieving doped regions, but also causing diffusion of dopants.
One proposed structure which allows for small device scaling while avoiding small scale source-drain extension formation problems is the elevated source-drain MOSFET, which also is called as raised source-drain MOSFET. One type of elevated source-drain MOSFET is the hot-carrier suppressed (HCS) MOSFET, a cross-section of which is shown in
FIG. 2
, that includes substrate
210
, gate dielectric
215
, gate conductor
220
and sidewall
270
. Besides, HCS MOSFET also has source and drain region
240
in substrate
210
.
Rather than using source-drain extension regions, the HCS MOSFET has elevated layers
250
which perform the same functions as source-drain extension regions in conventional MOSFETs but avoid the dopants diffusion problem in their formation. That is, layers
250
reduce, or suppress, hot-carrier injection. Further, in order to provide lower sheet and contact resistance, additional layers
260
are utilized. Herein, doping concentration of additional layers
260
is higher than that of elevated layers
250
. Besides, because many of the functions of the deep source-drain regions of conventional MOSFETs are fulfilled by the additional layer
260
, HCS MOSFET source and drain regions
240
can be remain shallow, which is desirable in forming smaller devices. More detailed information regarding the general structure and performance of HCS MOSFETs devices can be found in Shin et al., “MOSFET Drain Engineering Analysis for Deep-Submicrometer Dimensions: A New Structural Approach”, IEEE Transactions on Electron Devices, Vol. 39, No. 8 (August 1992).
While elevated source-drain MOSFETs have comparable performance characteristics to those of conventional MOSFETs while at the same time permitting the formation of smaller devices when compared with conventional MOSFETs, use of elevated source-drain MOSFETs has not become widespread. The devices are difficult to manufacture for al least following reasons. First, as shown in
FIG. 2
, elevated layers
250
and second layers
260
must be selectively grown, which is a difficult task involving high vacuum and chemical vapor deposition processes. Such processes further requires expensive equipment, are difficult to control, critically rely on surface preparation, and are cagily ruined by a small amount of contamination.
Second, source and drain regions
240
are doped using conventional methods, e.g. ion implantation, prior to forming elevated layers
250
and second layers
260
. For the same reasons that source-drain extension regions depth in a conventional MOSFET is difficult to control, so too is it difficulty to maintain shallow source and drain regions
240
, which are desirable in forming small scale elevated source-drain MOSFETs. Further, the heat cycles in both elevated layers
250
and second layers
260
formation cause the dopants to diffuse.
Third, qualify of sidewall
270
of elevated source-drain MOSFETs is generally lacking. Sidewalls of sufficient uniform thickness are necessary to control capacitance between gate the raise source-drain regions (layers
250
and
260
). Such sidewall
270
, however, are general grown or deposited on the gate prior to forming layers
260
/
260
, and the ability to form sidewalls of adequate uniform thickness to sufficiently control capacitance is extremely difficult (for example, shape of deposited sidewall
270
is fan-shape), particularly when subjected to the forming process of both layers
260
/
260
.
Moreover, because that metal silicide has been widespread used to reduced the resistance between the MOSFET and conductive lines, and also because an unavoidable problem is that thermal processes of formation of metal silicide further induces diffusion of doped dopants. It is crystal-clear that outline of shallow source and drain regions
240
is broaden, which is more strong when outline of shallow source and drain regions
240
has been broaden by thermal process of formation of both sidewall and layers
250
/
260
. Then, directly, qualify of the elevated source-drain MOSFET is further degraded by application of metal silicide.
Therefore, it is desirable to develop a process that will allow for easier manufacturabiliy of elevated source-drain MOSFETs, and thus allow for semiconductor device formation of reduced size.
SUMMARY OF THE INVENTION
Objects of the present invention at least include forming the elevated source-drain MOSFET without disadvantage of conventional fabrication of elevated source-drain MOSFET.
Objects of the present invention further comprise integrating forming processes of gate dielectric layer, elevated source-drain and metal silicide during fabrication of source-drain MOSFET.
Still an object of the invention is to present a new structure of the elevated source-drain MOSFET.
In short, one method present by the invention at least includes following basic steps: provides a substrate; covers part of the substrate by a doped amorphous silicon layer and covers part of the substrate by a first dielectric layer; forms a metal silicide layer on the doped amorphous silicon layer; removes the first dielectric layer to form a window; forms a second dielect

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