Fabrication of transistor contacts

Details Fabrication of transistor contacts Fabrication of transistor contacts

1992-11-27

1993-12-21

Quach, T. N.

Fishing, trapping, and vermin destroying

437162, 437191, 437193, H01L 21283, H01L 21225, H01L 21336

Patent

active

052720993

ABSTRACT:
The method of forming an integrated circuit field effect transistor having a gate electrode, source and drain elements with buried contacts to a silicon substrate. A gate silicon oxide layer is formed on the silicon substrate. An in-situ doped layer of polysilicon is formed over the gate silicon oxide layer. An opening is formed in the doped polysilicon layer and the silicon oxide layer to the silicon substrate at the location of the buried contacts. A layer of undoped polysilicon is deposited over the doped polysilicon layer and in the opening to the silicon substrate. Doping by ion implantation of the undoped polysilicon layer is done to form a doped polysilicon gate electrode/buried contact layer. The polysilicon gate electrode/buried contact layer is patterning and etching to form the gate electrode of said transistor and buried contact layer. The source and drain regions are implanted using said polysilicon gate electrode pattern as a mask. The structure is heated to form the buried contact to at least one of the source and drain regions. Alternatively, a contact to an existing device region within the substrate may be contacted using a similar multiple layer polysilicon method.

REFERENCES:
patent: 4516147 (1985-05-01), Komatsu et al.
patent: 4808555 (1989-02-01), Mauntel et al.
patent: 4901134 (1990-02-01), Misawa et al.
patent: 4966864 (1990-10-01), Pfierter
patent: 5030584 (1991-07-01), Nakata
patent: 5049514 (1991-09-01), Mozi
patent: 5168072 (1992-12-01), Moslehi

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