Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
2000-10-17
2002-09-17
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
C257S652000
Reexamination Certificate
active
06452285
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to a circuit device incorporating standardized contact defects and to methods of fabricating the same.
2. Description of the Related Art
Large scale integrated circuits now routinely contain millions of individual transistors and other electronic components. Most of the interconnections for the numerous individual components are provided via one or more metallization layers that serve as global interconnect levels. Each metallization layer is ordinarily deposited on the substrate of the integrated circuit as a single continuous layer that is thereafter patterned lithographically and etched to remove metal from areas where metal lines are not required.
In addition to the one or more metallization layers, modern integrated circuits also incorporate numerous routing-restricted interconnect levels commonly known as local interconnects and contacts. Local interconnects and contacts are used for short metallization runs such as those that locally interconnect gates and drains in NMOS and CMOS circuits and those that connect a given metallization layer to a particular structure in the integrated circuit.
A method frequently employed to form contact structures involves a damascene process in which the substrate containing the integrated circuit is coated with a layer of dielectric material that is lithographically patterned and etched to form contacts or vias in the dielectric layer where the contact structures will be formed. Thereafter, the contact material, or materials if a laminate structure is desired, is deposited over the dielectric layer. The goal of the deposition process is to fill the vias as completely as possible. Finally, a planarization process is performed to remove the excess conducting material from the dielectric layer and leave only the filled vias.
Accurate and reliable defect inspection is vital to successful semiconductor fabrication. Microelectronic circuit structures, such as contact structures, may be highly sensitive to contamination by particulates introduced by various semiconductor processing tools and to the various deleterious effects associated with unwanted residual films left over after semiconductor processing steps or unanticipated poor process control. Examples of process irregularities that contact formation may present are legion, and include such things as partially cleared contacts, partially or fully closed contacts, and scumming.
Currently, inspection for contact defects is performed with various types of scanning tools. Some of these employ optical scanning, while others utilize laser scanning. Many conventional contact defect scanning techniques utilize die-to-die comparison, although die-to-database comparing is also sometimes used.
A difficulty associated with conventional contact defect scanning is tool calibration. In order for a given inspection tool to be able to accurately identify and characterize contact defects, the inspection tool must be instructed or otherwise programmed to scan in certain locations on the wafer for certain features that are indicative of a defect. For contact defect inspection, the task of tool calibration has proved to be difficult. The problem stems from the fact that both the contacts and the defects come in a variety of geometries. This lack of a standard geometry from which to calibrate the inspection tool means that tool calibration for parameters such as optimum depth of focus may involve some degree of experimentation. Accordingly, where the contact formation process is changed, the trial and error method of calibration must be repeated.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, a circuit device is provided that includes a substrate and an insulating film positioned on the substrate that has a plurality of openings therein. A plurality of members is provided. Each of the plurality of members is positioned in one of the plurality of openings and has known dimensions. The plurality of members provide a known set of defects in the plurality of openings to facilitate inspection of the plurality of openings.
In accordance with another aspect of the present invention, a test circuit device is provided that includes a substrate and an insulating film positioned on the substrate that has a plurality of openings therein. A plurality of metal pegs is provided. Each of the plurality of metal pegs is positioned in one of the plurality of openings and has known dimensions. The plurality of metal pegs provide a known set of defects in the plurality of openings to facilitate inspection of the plurality of openings.
In accordance with another aspect of the present invention, a method of fabricating a circuit device on a substrate is provided that includes forming a plurality of members on the substrate, each with known dimensions and an upper surface. An insulating film is formed over the members and openings in the insulating film are formed to expose at least the upper surfaces of the plurality of members.
In accordance with another aspect of the present invention, a method of inspecting a first plurality of contacts in an insulating film for defects utilizing an inspection tool is provided. The method includes forming a plurality of members in a second plurality of contacts. The plurality of members have known dimensions. The inspection tool is calibrated using the plurality of members as a known set of defects in the second plurality of contacts. Thereafter, the first plurality of contacts is inspected using the calibrated inspection tool.
REFERENCES:
patent: 4473795 (1984-09-01), Wood
patent: 5004340 (1991-04-01), Tullis et al.
patent: 5508800 (1996-04-01), Miyashita
patent: 5691812 (1997-11-01), Bates et al.
patent: 5815275 (1998-09-01), Svetkoff et al.
patent: 6274396 (2001-08-01), Funsten
Stanley Wolf and Richard N. Tauber; Silicon Processing for the VLSI Era, vol. 2—Process Integration; pp. 87-110; 1990.
Cooper David
McCarthy Michael
Honeycutt Timothy M.
Meier Stephen D.
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