Fabrication of stacked MOS devices utilizing lateral seeding and

Details Fabrication of stacked MOS devices utilizing lateral seeding and Fabrication of stacked MOS devices utilizing lateral seeding and

1984-05-17

1987-03-24

Saba, William G.

Metal working

Method of mechanical manufacture

Assembling or joining

29571, 29576B, 29576E, 29576T, 29578, 29580, 148 15, 148175, 148DIG91, 148DIG164, 156612, 357 237, 357 239, 357 42, 357 59, H01L 21324, H01L 2136

Patent

active

046514082

ABSTRACT:
In a process for manufacturing vertically integrated MOS devices and circuits, gate oxide and a gate are formed on a semiconductor substrate such as a silicon substrate. A layer of polysilicon is then deposited over the wafer, the polysilicon contacting the substrate silicon through a window in the gate oxide. The substrate silicon and the polysilicon are then laser melted and cooled under conditions that encourage crystal seeding from the substrate into the polysilicon over the gate. Subsequently, ions are implanted into the silicon substrate and the polysilicon to form source and drain regions. By introducing the source and drain dopants after melt associated seeding of the polysilicon, the risk of dopant diffusion into the device channel regions is avoided.

REFERENCES:
patent: 4467518 (1984-08-01), Bansal et al.
patent: 4476475 (1984-10-01), Naem et al.
patent: 4487635 (1984-12-01), Kugimiya et al.
patent: 4488348 (1984-12-01), Jolly
patent: 4500905 (1985-02-01), Shibata
patent: 4523370 (1985-06-01), Sullivan et al.
patent: 4555843 (1985-12-01), Malhi
Douglas, J. H., "The Route to 3-D Chips" High Technology, Sep. 1983, pp. 55-59.

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