Fabrication of solid-state imaging device having no transfer...

Semiconductor device manufacturing: process – Making device or circuit responsive to nonelectrical signal

Reexamination Certificate

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Details

C438S060000, C438S075000

Reexamination Certificate

active

06194242

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a solid-state imaging device and more particularly, to a two-dimensional solid-state imaging device that prevents transmission errors during a signal-charge transfer process from vertical charge-transfer sections to a horizontal charge-transfer section, and a fabrication method of the device.
2. Description of the Prior Art
FIG. 1
schematically shows a plan view of one of photoelectric conversion sections and its neighborhood of a conventional two-dimensional solid-state imaging device of the progressive-scan interline-transfer type.
FIGS. 2 and 3
schematically show cross-sectional views along the lines II—II and III—III in
FIG. 1
, respectively.
FIG. 4
schematically shows a plan view of an interconnection area between one of single-channel vertical charge-transfer sections and a single-channel horizontal charge-transfer section.
FIGS. 5 and 6
schematically show cross-sectional views along the lines V—V and VI—VI in
FIG. 4
, respectively.
As shown in
FIGS. 1 and 4
, rectangular photoelectric conversion sections
151
are arranged in a matrix array. Elongated vertical charge-transfer sections
152
are arranged along the respective columns of the matrix array. An elongated horizontal charge-transfer section
153
is disposed at the output-side ends of the vertical charge-transfer sections
152
to extend along the rows of the matrix array. An output section, which is disposed at the output-side end of the horizontal charge-transfer section
153
, is not shown here.
Each of the vertical charge-transfer sections
152
is formed by a vertical Charge-Coupled Device (CCD) register. The horizontal charge-transfer section
153
is formed by a horizontal CCD register.
As shown in
FIGS. 2
,
3
,
5
, and
6
, p-type wells
102
,
103
, and
104
are formed in a surface region of an n-type silicon substrate
101
. The elongated p-type well
102
is formed in the horizontal charge-transfer section
153
to extend along the section
153
. The rectangular p-type wells
103
are located in the respective photoelectric conversion sections
151
. The elongated p-type wells
104
are located in the respective vertical charge-transfer sections
152
to extend along the corresponding sections
152
.
The p-type wells
102
in the horizontal charge-transfer section
153
have a depth large enough for preventing the punch-through phenomenon from occurring in source/drain regions of Metal-oxide-Semiconductor Field-Effect Transistors (MOSFETs) provided in the output section. The p-type wells
102
is deeper than the p-type wells
103
and
104
. The p-type wells
102
have a doping concentration lower than that of the p-type wells
104
for the purpose of allowing to drive the horizontal charge-transfer section
153
by using a low-voltage and high-frequency driving signal.
The p-type wells
103
in the photoelectric conversion sections
151
have a low doping concentration to allow the so-called “electronic shutter” operation, which is defined as an operation that the signal charges stored in photodiodes
130
in the sections
151
are transferred to the remaining substrate
101
when a specific voltage is applied to the substrate
101
.
The p-type wells
104
in the vertical charge-transfer sections
152
have a higher doping concentration than that of the wells
103
so that the signal charges in the vertical charge-transfer sections
152
do not flow into the remaining substrate
101
at the time the electronic shutter operation is performed.
In the photoelectric conversion sections
151
, as shown in
FIGS. 1 and 2
, rectangular n-type diffusion regions
108
are formed in the respective p-type wells
103
. Each of the n-type diffusion regions
108
and a corresponding one of the remaining p-type wells
103
constitute the photodiode
130
.
In the vertical charge-transfer sections
152
, as shown in
FIGS. 1
to
3
, elongated n-type buried channel regions
105
are formed in the respective p-type wells
104
to extend along the corresponding wells
104
.
In the horizontal charge-transfer sections
153
, as shown in
FIGS. 4 and 5
, n-type buried channel regions
106
and
107
are formed in the p-type well
102
. The buried channel regions
106
and
107
are alternately arranged along the well
102
. The buried channel regions
106
serve as charge-storage regions for storing the signal charges. The buried channel regions
107
serve as charge-barrier regions for confining the signal charges in the adjoining charge-storage regions.
The n-type buried channel regions
106
have a doping concentration slightly greater than that of the n-type buried channel regions
107
. The doping concentrations of the n-type buried channel regions
106
and
107
, which are determined according to the doping concentration of the corresponding p-type well
102
, are less than that of the n-type buried channel regions
105
.
P-type diffusion regions
109
and
110
are formed in the surface region of the substrate
101
at the respective interfaces between the p-type wells
103
and
104
, as shown in FIG.
2
. The p-type diffusion regions
109
serve as channel stops. The p-type diffusion regions
110
serve as parts of read-out gates for transferring the signal charges in the photodiodes
130
to the corresponding vertical charge-transfer sections
152
. The p-type diffusion regions
109
have a high doping concentration. The p-type diffusion regions
110
have a low doping concentration.
A gate oxide film
111
is formed on the surface of the substrate
101
to cover the photoelectric conversion sections
151
, the vertical charge-transfer sections
152
, and the horizontal charge-transfer section
153
.
First, second, and third patterned polysilicon films
112
,
113
, and
114
are formed on the gate oxide film
111
in the photoelectric conversion sections
151
and the vertical and horizontal charge-transfer sections
152
and
153
. These polysilicon films
112
,
113
, and
114
serve as gate electrodes and wiring lines. Parts of the polysilicon films
112
,
113
, and
114
which are contacted with the gate oxide film
111
serve as the gate electrodes. Parts of the polysilicon films
112
,
113
, and
114
which are not contacted with the gate oxide film
111
serve as the wiring lines.
The p-type diffusion region
110
, the corresponding gate electrode, and the gate oxide film
111
in each of the photoelectric conversion sections
151
constitute the read-out gate. The buried channel region
105
, the corresponding gate electrodes, and the gate oxide film
111
in each of the vertical charge-transfer sections
152
constitute the vertical CCD register driven by a four-phase driving signal. The buried channel region
102
, the corresponding gate electrodes, and the gate oxide film
111
in the horizontal charge-transfer section
153
constitute the horizontal CCD register driven by a two-phase driving signal.
In the vertical and horizontal charge-transfer sections
152
and
153
, the second polysilicon film
113
is partially overlapped with the underlying first polysilicon film
112
. Further, the third polysilicon film
114
is partially overlapped with the underlying first and second polysilicon films
112
and
113
. The second polysilicon film
113
is electrically insulated from the first polysilicon film
112
by an intervening gate oxide film
111
a
. The third polysilicon film
114
is electrically insulated from the underlying first polysilicon film
112
by the gate oxide film
111
a
and from the underlying second polysilicon film
113
by a gate oxide film
111
b.
An interlayer insulating film
115
is formed to cover the first, second, and third polysilicon films
112
,
113
, and
114
in the photoelectric conversion sections
151
and the vertical and horizontal charge-transfer sections
152
and
153
.
A metal film
116
is formed on the interlayer insulating film
115
in the photoelectric conversion sections
151
and the vertical and horizontal charge-transfer sections
152
and
153

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