Fabrication of silicon-on-nothing (SON) MOSFET fabrication...

Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching

Reexamination Certificate

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C438S142000, C438S411000, C438S421000, C438S694000, C438S700000, C438S703000, C438S749000

Reexamination Certificate

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07015147

ABSTRACT:
A method for fabrication of silicon-on-nothing (SON) MOSFET using selective etching of Si1−xGexlayer, includes preparing a silicon substrate; growing an epitaxial Si1−xGexlayer on the silicon substrate; growing an epitaxial thin top silicon layer on the epitaxial Si1−xGexlayer; trench etching of the top silicon and Si1−xGex, into the silicon substrate to form a first trench; selectively etching the Si1−xGexlayer to remove substantially all of the Si1−xGexto form an air gap; depositing a layer of SiO2by CVD to fill the first trench; trench etching to from a second trench; selectively etching the remaining Si1−xGexlayer; depositing a second layer of SiO2by CVD to fill the second trench, thereby decoupling a source, a drain and a channel from the substrate; and completing the structure by state-of-the-art CMOS fabrication techniques.

REFERENCES:
patent: 6537894 (2003-03-01), Skotnicki et al.
patent: 6713356 (2004-03-01), Skotnicki et al.
patent: 2004/0235262 (2004-11-01), Lee et al.
patent: 2799307 (2001-04-01), None
patent: WO200057480 (2000-09-01), None
“Silicon On Nothing (SON)-Fabrication, Material and Devices”; Proceedings-Electrochemical Society vol. 2001-3; (2001') pp. 391-402; Skotnicki.
M. Jurczak et al.,SON(Silicon on Nothing)—A New Device Architecture for the ULSI Era, VLSI Tech. Dig., p. 29, (1999).
R. Koh,Buried Layer Engineering to Reduce the Drain-Induced Barrier Lowering of Sub-0.05um SOI-MOSFETJpn. J. Appl. Phys., vol. 38, p. 2294 (1999).
M. Jurczak, et al.,Silicon-on-Nothing(SON)—an innovative Process for Advanced CMOS, IEEE Trans. El. Dev. Vol. 47, pp 2179-2187 (2000).
R. Chau et al.,A 50 nm Depleted-Substrate CMOS Transistor, IEDM, p. 621, 2001.
T. Sato et al.,SON(Silicon on Nothing)MOSFET Using ESS(Empty Space in Silicon)Technique for SoC Application, IEDM, p. 809, 2001.

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