Fabrication of semiconductor interconnect structure

Semiconductor device manufacturing: process – Chemical etching – Liquid phase etching

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S745000, C216S100000

Reexamination Certificate

active

07972970

ABSTRACT:
An etching process for selectively etching exposed metal surfaces of a substrate and forming a conductive capping layer over the metal surfaces is described. In some embodiments, the etching process involves oxidation of the exposed metal to form a metal oxide that is subsequently removed from the surface of the substrate. The exposed metal may be oxidized by using solutions containing oxidizing agents such as peroxides or by using oxidizing gases such as those containing oxygen or ozone. The metal oxide produced is then removed using suitable metal oxide etching agents such as glycine. The oxidation and etching may occur in the same solution. In other embodiments, the exposed metal is directly etched without forming a metal oxide. Suitable direct metal etching agents include any number of acidic solutions. The process allows for controlled oxidation and/or etching with reduced pitting. After the metal regions are etched and recessed in the substrate surface, a conductive capping layer is formed using electroless deposition over the recessed exposed metal regions.

REFERENCES:
patent: 4002778 (1977-01-01), Bellis et al.
patent: 4181760 (1980-01-01), Feldstein
patent: 4311551 (1982-01-01), Sykes
patent: 4737446 (1988-04-01), Cohen et al.
patent: 4981725 (1991-01-01), Nuzzi et al.
patent: 5151168 (1992-09-01), Gilton et al.
patent: 5318803 (1994-06-01), Bickford et al.
patent: 5380560 (1995-01-01), Kaja et al.
patent: 5382447 (1995-01-01), Kaja et al.
patent: 5486234 (1996-01-01), Contolini et al.
patent: 5576052 (1996-11-01), Arledge et al.
patent: 5674787 (1997-10-01), Zhao et al.
patent: 5695810 (1997-12-01), Dubin et al.
patent: 5770095 (1998-06-01), Sasaki et al.
patent: 5824599 (1998-10-01), Schacham-Diamond et al.
patent: 5891513 (1999-04-01), Dubin et al.
patent: 5897375 (1999-04-01), Watts et al.
patent: 5913147 (1999-06-01), Dubin et al.
patent: 5969422 (1999-10-01), Ting et al.
patent: 5972192 (1999-10-01), Dubin et al.
patent: 6065424 (2000-05-01), Shacham-Diamand et al.
patent: 6136707 (2000-10-01), Cohen
patent: 6139763 (2000-10-01), Ina et al.
patent: 6174353 (2001-01-01), Yuan et al.
patent: 6184124 (2001-02-01), Hasegawa et al.
patent: 6197181 (2001-03-01), Chen
patent: 6197364 (2001-03-01), Paunovic et al.
patent: 6270619 (2001-08-01), Suzuki et al.
patent: 6309981 (2001-10-01), Mayer et al.
patent: 6329284 (2001-12-01), Maekawa
patent: 6342733 (2002-01-01), Hu et al.
patent: 6355153 (2002-03-01), Uzoh et al.
patent: 6394114 (2002-05-01), Gupta
patent: 6398855 (2002-06-01), Palmans et al.
patent: 6524167 (2003-02-01), Tsai et al.
patent: 6537416 (2003-03-01), Mayer et al.
patent: 6586342 (2003-07-01), Mayer et al.
patent: 6645567 (2003-11-01), Chebiam et al.
patent: 6664122 (2003-12-01), Andryuschenko et al.
patent: 6692546 (2004-02-01), Ma et al.
patent: 6692873 (2004-02-01), Park
patent: 6713122 (2004-03-01), Mayer et al.
patent: 6716753 (2004-04-01), Shue et al.
patent: 6775907 (2004-08-01), Boyko et al.
patent: 6815349 (2004-11-01), Minshall et al.
patent: 6884724 (2005-04-01), Hsu et al.
patent: 6887776 (2005-05-01), Shang et al.
patent: 6975032 (2005-12-01), Chen et al.
patent: 7008871 (2006-03-01), Andricacos et al.
patent: 7049234 (2006-05-01), Cheng et al.
patent: 7056648 (2006-06-01), Cooper et al.
patent: 7124386 (2006-10-01), Smith et al.
patent: 7217649 (2007-05-01), Bailey et al.
patent: 7262504 (2007-08-01), Cheng et al.
patent: 7285494 (2007-10-01), Cheng et al.
patent: 7338908 (2008-03-01), Koos et al.
patent: 7531463 (2009-05-01), Koos et al.
patent: 7605082 (2009-10-01), Reid et al.
patent: 7811925 (2010-10-01), Reid et al.
patent: 2001/0038448 (2001-11-01), Jun et al.
patent: 2002/0084529 (2002-07-01), Dubin et al.
patent: 2003/0001271 (2003-01-01), Uozumi
patent: 2003/0003711 (2003-01-01), Modak
patent: 2003/0059538 (2003-03-01), Chung et al.
patent: 2003/0075808 (2003-04-01), Inoue et al.
patent: 2003/0176049 (2003-09-01), Hegde et al.
patent: 2003/0190426 (2003-10-01), Padhi et al.
patent: 2004/0065540 (2004-04-01), Mayer et al.
patent: 2004/0253740 (2004-12-01), Shalyt et al.
patent: 2005/0074967 (2005-04-01), Kondo et al.
patent: 2005/0158985 (2005-07-01), Chen et al.
patent: 2005/0250339 (2005-11-01), Shea et al.
patent: 2005/0266265 (2005-12-01), Cheng et al.
patent: 2006/0205204 (2006-09-01), Beck
patent: 2007/0105377 (2007-05-01), Koos et al.
patent: 2008/0286701 (2008-11-01), Rath
patent: 2010/0015805 (2010-01-01), Mayer et al.
patent: 2011/0056913 (2011-03-01), Mayer et al.
patent: 02111883 (1990-04-01), None
patent: 03122266 (1991-05-01), None
patent: 99/47731 (1999-09-01), None
patent: 2009/023387 (2009-02-01), None
U.S. Final Office Action (Jun. 12, 2008) from U.S. Appl. No. 11/586,394.
Reid et al., “Capping Beofre Barrier-Removal IC Fabrication Method,” Novellus Systems, Inc., U.S. Appl. No. 12/184,145, filed Jul. 31, 2008.
Notice of Allowance mailed Mar. 13, 2009 for U.S. Appl. No. 11/586,394 and Allowed Claims.
Notice of Allowance mailed Jun. 11, 2010 for U.S. Appl. No. 12/184,145 and Allowed Claims.
U.S. Final Office Action, mailed Jun. 12, 2008 from U.S. Appl. No. 11/586,394.
Patri et al., Role of the Fuctional Groups of Complexing Agents in Copper Slurries, Journal of The Electrochemical Society, 153 (7) G650-G659 (2006).
Choi et al, Dissolution Behaviors of Copper Metal in Alkaline H2O2-EDTA Solutions, Journal of Nuclear Science and Technology, 30(6), pp. 549-553 (Jun. 1993).
Aksu et al., Electrochemistry of Copper in Aqueous Ethylenediamine Solutions, Journal of The Electrochemical Society, 149 (7) B340-B347 (2002).
U.S. Patent Application entitled “Fabrication of Semiconductor Interconnect Structure”, U.S. Appl. No. 11/888,312, filed Jul. 30, 2007.
U.S. Appl. No. 12/462,424, filed Aug. 4, 2009.
Mukherjee et al., “Planarization of Copper Damascene Interconnects by Spin-Etch Process: A Chemical Approach”, Mat. Res. Soc. Symp. vol. 612 © 2000 Materials Research Society, year of 2000.
Reid et al., “Capping Before Barrier-Removal IC Fabrication Method”, Novellus Systems, Inc., U.S. Appl. No. 12/875,857, filed Sep. 3, 2010.
Office Action dated Apr. 1, 2011 for Korean Patent Application No. 10-2009-0067246.
U.S. Office Action mailed Jan. 23, 2007, from U.S. Appl. No. 11/251,353.
Andryuschenko et al., “Electroless and Electrolytic Seed Repair Effects on Damascene Feature Fill,” Proceedings of International Interconnect Tech. Conf., San Francisco Ca., Jun. 4-6, 2001, pp. 33-35.
Chen et al., “ECD Seed Layer for Inlaid Copper Metallisation,” Semiconductor Fabtech—12thEdition, 5 Pages, Jul. 2000.
Ken M. Takahashi, “Electroplating Copper into Resistive Barrier Films,” Journal of the Electrochemical Society, 147 (4) 1417-1417 (2000).
T.P. Moffat et al., “Superconformal Electrodeposition of Copper in 500-90 nm Features,” Journal of the Electrochemical Society, 147 (12) 4524-4535 (2000).
Ritzdorf et al., “Electrochemically Deposited Copper,” Conference Proceedings ULSI XV 2000, Materials Research Society, 101-107.
Reid et al., “Optimization of Damascene Feature Fill for Copper Electroplating Process,” Shipley Company, IITC 1999, 3 Pages.
Reid et al., “Copper PVD and Electroplating,” Solid State Technology, Jul. 2000, www.solid-state.com, 86-103.
Reid et al., “Factors Influencing Fill of IC Features Using Electroplated Copper,” Adv Met Conf Proc 1999, MRS 10 Pages, (2000).
Shacham-Diamond et al., “Copper Electroless Deposition Technology for Ultr-Large-Scale-Integration (ULSI) Metallization,” Microelectronic Engineering 33 (1997) 47-58.
Hu et al., “Effects of Overlayers on Electromigration Reliability Improvement for Cu/Low K Interconnects,” Presented in the Proceedings of the 42ndAnnual IRPS held Apr. 25-29, 2004, p. v, article published May 28, 2004, 7 Pages.
Hu et al., “Reduced Electromigration of Cu Wires by Surface Coating,” Applied Physics Letters, vol. 81, No. 10, (2002), 1782-1784.
Park et al., “Electro

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Fabrication of semiconductor interconnect structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fabrication of semiconductor interconnect structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fabrication of semiconductor interconnect structure will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2717146

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.