Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – And gettering of substrate
Reexamination Certificate
2000-07-31
2003-01-21
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
And gettering of substrate
C438S424000, C438S433000, C438S440000, C438S524000, C438S525000, C438S526000
Reexamination Certificate
active
06509248
ABSTRACT:
BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to semiconductor devices. More particularly, the present invention relates to semiconductor gettering structures and methods of forming them. One embodiment of the present invention relates to ion-implanted gettering structures that are implanted substantially below the bottom of isolation trenches.
2. The Relevant Technology
In the microelectronics industry, a substrate refers to one or more semiconductor layers or structures which includes active or operable portions of semiconductor devices. In the context of this document, the term “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term substrate refers to any supporting structure including but not limited to the semiconductive substrates described above.
The ever-present pressure upon the microelectronics industry to shrink electronic devices and to crowd a higher number of electronic devices onto a single die, called miniaturization, has required development of isolation trenches to replace such structures as local oxidation of silicon (LOCOS) regions. As miniaturization continues to shrink dimensions of electronic devices, limitations on the ability to restrict chemical impurities in the fabrication process are being reached. To compensate for such chemical impurities limitations, gettering structures are formed within semiconductive devices that have an affinity for chemical impurities.
One prior art method of forming a gettering structure is blanket implantation of ions within the semiconductive substrate as illustrated in
FIG. 1
so as to damage the material of the semiconductive substrate. In
FIG. 1
it can be seen that a semiconductor structure
10
includes a substrate
12
, preferably composed of a semiconductor material, such as silicon or germanium, and having an upper surface
26
and an oxide layer
14
thereupon. Blanket implantation of semiconductor structure
10
is illustrated wherein a gettering structure
32
comprises damaged silicon created by ions that have been implanted with mega electron volt (MeV) implantation equipment. As referred to herein, KeV implantation equipment can implant with energy in a range from about 25 Kev to about 600 Kev, and MeV implantation equipment can implant with energy in a range from about 25 Kev to about 2800 Kev. Damage is contained within gettering structure
32
which is at a depth d. Blanket implantation, however, causes damage in the semiconductive materials within gettering structure
32
. A diode junction
42
is seen below region
40
which adjacent to active area
20
and field oxide region
15
which can be formed by LOCOS processing.
Gettering structure
32
includes substantial disturbance of the monocrystalline lattice of the semiconductive material that not only compromises the semiconductive integrity of semiconductor substrate
12
, but also allows contaminants to migrate and be captured within gettering structure
32
. Attempts to improve the gettering efficiency of gettering structure
32
, such as heat treating, may be constrained by the allowable thermal budget in a given process.
Lattice vacancies and crystal originated pits (COPs) often form during the crystal pulling process. COPs both disturb the integrity of a semiconductor device due to surface pits. Self implantation of interstitials into region
30
seen in
FIGS. 1 and 2
, such as with silicon, can reduce the size of the surface pits or eliminate them with an anneal adequate thermal cycle.
Another way to form gettering structure
32
is to use a mask
18
, as seen in
FIG. 2
, to keep the gettering implanted materials away from regions that will cause leakage or other problems, for example at an N-well edge. Mask
18
, however, adds cost to the process.
FIG. 2
illustrates the prior art method of implantation of a gettering structure
32
through a mask
18
. It can been seen that a semiconductor structure
10
includes a substrate
12
composed of a semiconductor material such as silicon or germanium, an oxide layer
14
, and mask
18
. It can been seen that mask
18
has been patterned to form an implant corridor
22
through which ions may be implanted into substrate
12
. Also shown is a bottom
38
of active area
20
below mask
18
. A detriment of the structure see in
FIG. 2
is the capital and energy requirements in masking the structure prior to implanting gettering structure
32
.
Another problem of forming a gettering layer is the energy and equipment cost of using KeV implantation equipment versus MeV implantation equipment. KeV implantation equipment, which implants close to the surface of implantation, incurs a greater risk of defects close to the surface of implantation. Conversely, MeV implantation equipment can implant farther away from the surface of implantation than KeV implantation equipment and therefor has less of a risk of defects close to the surface of implantation. The cost of KeV implantation equipment is less than that of MeV implantation equipment.
Gettering structure
32
has a shape that has an initial width equivalent to the width of an implant corridor
22
and a final width W that is formed naturally by spreading implanted species. Region
30
may cause contaminants to be more mobile through the damaged lattice therein. Gettering structure
32
is required to be formed at a depth d, seen in
FIG. 1
, that is sufficiently beneath active area
20
such that metallic contaminants do not encroach therewithin.
What is needed is a method of forming a semiconductor gettering structure that avoids the problems of the prior art. In particular, what is needed is a method of forming a semiconductor gettering structure by ion implantation that minimizes crystal lattice dislocations caused by ion implantation. What is also needed is a method of forming a semiconductor gettering structure that uses less capital and energy cost than that which was used in the prior art.
SUMMARY OF THE INVENTION
The present invention relates to the formation of a gettering structure by ion implantation. Formation of a gettering structure is carried out by ion implantation of a material that has an affinity for impurities such as metals. Iron is a typical metal impurity. The ion implantation material may be such elements as oxygen, silicon, germanium, and equivalents. Ion implantation is carried out using high current implantation techniques that are known in the art.
A preferred embodiment of the present invention includes forming a recess in a semiconductive substrate within active areas that border on the recess. The recess is preferably formed by using a reactive anisotropic etching medium. Next, ions are implanted by changing the ion implantation process for a process for a reactive anisotropic etching medium The inventive method creates separate gettering regions beneath the recess without causing substantial damage within active areas that border on the recess.
An advantage of the method of the present invention is that semiconductor gettering structures are formed without a masking procedure. Additionally, the inventive method can use KeV implantation equipment and processes, although more expensive MeV implantation equipment can also be used. Metallic contaminants will diffuse freely through the semiconductive substrate to any depth. Another advantage of the present invention is that lateral spread of ions that cause damage in the semiconductor substrate during implantation is reduced due to the lower energy KeV implantation of high current implantation as opposed to MeV implantation. Also, the lateral spread of ions during implantation is reduced due to a shallower implantation depth when using the lower energy KeV implantation of high current implantations.
Following implantation and formatio
Micro)n Technology, Inc.
Nguyen Khiem
Pham Long
Workman & Nydegger & Seeley
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