Fabrication of oxide regions having multiple thicknesses using m

Details Fabrication of oxide regions having multiple thicknesses using m Fabrication of oxide regions having multiple thicknesses using m

1999-02-23

2000-10-17

Bowers, Charles

Semiconductor device manufacturing: process

Utilizing varying dielectric thickness

438275, H01L 218234

Patent

active

061331643

ABSTRACT:
The present invention is a method for fabricating a plurality of oxide regions having a plurality of thicknesses on a semiconductor wafer. The present invention includes a step of depositing a first masking layer on the semiconductor wafer, and the first masking layer defines at least one first region for oxide growth of a first thickness. The present invention also includes a step of implanting oxygen ions into the at least one first region such that the first thickness of oxide on the at least one first region is relatively thicker. The first masking layer is then removed from the semiconductor wafer. The present invention further includes a step of depositing a second masking layer on the semiconductor wafer, and the second masking layer defines at least one second region for oxide growth of a second thickness. The present invention also includes a step of implanting nitrogen ions into the at least one second region such that the second thickness of oxide on the at least one second region is relatively thinner. The second masking layer is then removed from the semiconductor wafer. The present invention further includes the step of growing oxide on the at least one first region to have the first thickness and on the at least one second region to have the second thickness with a thermal process for the semiconductor wafer. During the thermal process, at least one third region of oxide may be grown to have a third thickness which is thinner than the oxide on the at least one first region and that is thicker than the oxide on the at least one second region since the at least one third region has not been exposed to oxygen ion implantation nor to nitrogen ion implantation.

REFERENCES:
patent: 5595922 (1997-01-01), Tigelaar et al.
patent: 5861347 (1999-01-01), Maiti et al.
patent: 5918116 (1999-06-01), Chittipeddi
patent: 5920779 (1999-07-01), Sun et al.
C.T. Liu, E.J. Lloyd, Yi Ma, M. Du, R.L. Opila, and S.J. Hillenius, High Performance 0.2 .mu.m CMOS with 25 .ANG. Gate Oxide Grown on Nitrogen Implanted Si Substrates, IEDM, 1996 pp. 499-502.
Y.C. King, C. Kuo, T.J. King, and C. Hu, Sub-5nm Multiple-Thickness Gate Oxide Technology using Oxide Implantation, IEDM, 1998, pp. 585-588.

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