Fabrication of MOS integrated circuit devices

Details Fabrication of MOS integrated circuit devices Fabrication of MOS integrated circuit devices

1983-02-18

1984-05-29

Weisstuch, Aaron

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 148 15, 148187, H01L 2174, H01L 21265

Patent

active

044506201

ABSTRACT:
In an MOS integrated circuit device, a multilayer polysilicon/metallic-silicide gate-level metallization structure is patterned to form gates and associated interconnects. Some of the interconnects are designed to make contact with ohmic regions in the single-crystalline body of the device. In accordance with a simplified fabrication procedure, a single implantation step is utilized to dope the metallic silicide while doping selected portions of the body. During a subsequent heating step, source, drain and ohmic contact regions are formed in the body. During the same step, the dopant in the metallic silicide diffuses into underlying layers of polysilicon and into body portions directly underlying polysilicon in amounts sufficient to render the polysilicon conductive and to form additional ohmic contact regions in the body.

REFERENCES:
patent: 4180596 (1979-12-01), Crowder et al.
patent: 4276688 (1981-07-01), Hsu
patent: 4329706 (1982-05-01), Crowder et al.
patent: 4339869 (1982-07-01), Reihl et al.
patent: 4343082 (1982-08-01), Lepselter et al.

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