Fabrication of metal interconnect for semiconductor device

Details Fabrication of metal interconnect for semiconductor device Fabrication of metal interconnect for semiconductor device

1987-04-09

1989-01-10

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437189, 437195, H01L 21441, H01L 21443

Patent

active

047973757

ABSTRACT:
Disclosed is a method of fabricating a semiconductor device comprising the step of defining metal interconnect features in a metal layer so that a metal feature having a size substantially larger than a predetermined feature size comprises an array of metal features. Each of the metal features in the array has a size not substantially larger than the predetermined feature size.

REFERENCES:
patent: 3983022 (1976-09-01), Auyang et al.
Adams, A. C., Bell Laboratories, "Plasma Planarization," Solid State Technology, Apr. 1981, pp. 178-181.
Ting, C. Y., Vivalda, V. J., and Schaefer, H. G., "Study of Planarized Sputter-Deposited SiO.sub.2," IBM System Products Division, J. Vac. Sci. Technol., 15(3), May/Jun., 1978, pp. 1105-1112.

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