Fabrication of interpoly dielctric for EPROM-related technologie

Fishing – trapping – and vermin destroying

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437195, 437920, 437978, H01L 21265, H01L 2176

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051048191

ABSTRACT:
A method and a device formed by the method of forming a composite dielectric structure between the floating polysilicon electrode and the control electrode of an EPROM-type device is disclosed. The dielectic is characterized by a thin (0-80 angstroms) thermally-grown or CVD bottom oxide layer covered by a relatively thin (<200 angstroms) silicon nitride layer. The top layer comprises a CVD oxide deposited in a thickness up to 150 angstroms. The capacitively measured effective thickness of the complete structure is about 200 .ANG. or less. The top layer CVD oxide has a thickness greater than the bottom oxide layer and greater than or equal to that of the silicon nitride layer and may also extend beyond the EPROM cell to form at least a part of the peripheral transistor dielectric.

REFERENCES:
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patent: 4616402 (1986-10-01), Mori
patent: 4630086 (1986-12-01), Sato et al.
patent: 4720323 (1988-01-01), Sato
patent: 4769340 (1988-09-01), Chang et al.
patent: 4808261 (1989-02-01), Ghidini et al.
patent: 4926222 (1990-05-01), Kosa et al.
patent: 4943836 (1990-07-01), Mori
"Determination of the Fowler-Nordheim Tunneling Barrier from Nitride to Oxide in Oxide:Nitride Dual Dielectric", by Leo D. Yau, IEEE Electron Device Letters, vol. EDL-7, No. 6, Jun., 1986; pp. 365-367.
S. Mori et al., "Novel Process and device technologies for submicron 4 Mb CMOS EPROMS", 1987 International Electron Devices Meeting, IEDM, Dec. 1987.

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