Fabrication of interlayer conductive paths in integrated circuit

Details Fabrication of interlayer conductive paths in integrated circuit Fabrication of interlayer conductive paths in integrated circuit

1988-05-23

1989-06-27

Walton, Donald L.

Fishing, trapping, and vermin destroying

437196, 437194, 357 65, 357 71, H01L 2144, H01L 2188

Patent

active

048430340

ABSTRACT:
A method of producing interlayer conductive paths having substantially planar top surfaces in a multilayer integrated circuit structure, comprising the steps of forming elements of either a conductive or semiconductive material as a lower layer, depositing an insulative layer on top of the lower layer elements, implanting ions into one or more selected regions of the insulative layer, forming at least one upper conductor over the selected regions and sintering the integrated circuit structure sufficient to render the selected regions conductive. The invention also embraces an integrated circuit structures with interlayer conductive paths made in accordance with this method.

REFERENCES:
patent: 3806361 (1974-04-01), Lehner
patent: 4222165 (1980-09-01), Hartman et al.
patent: 4425700 (1984-01-01), Sasaki et al.
patent: 4585490 (1986-04-01), Raffel et al.
patent: 4663826 (1987-05-01), Baeuerle
patent: 4722913 (1988-12-01), Miller
T. O. Herndon, "Present and Future Requirements for IC Multilevel Interconnect," 166th Meeting of Electrochemical Society, Oct. 7-12, 1984.

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