Fabrication of integrated circuits containing enhancement-mode F

Details Fabrication of integrated circuits containing enhancement-mode F Fabrication of integrated circuits containing enhancement-mode F

1976-07-02

1978-04-25

Rutledge, L. Dewayne

Metal working

Method of mechanical manufacture

Assembling or joining

29577R, 29578, 148 15, 148187, 156653, 156655, 156657, 156659, 156662, 357 23, 357 41, 357 42, 357 51, 357 59, H01L 2128, H01L 2978, B01J 1700

Patent

active

040854981

ABSTRACT:
Enhancement-mode field-effect transistors (FETs) and depletion-mode FETs are provided on the same semiconductive substrate using five basic, lithographic, pattern-delineating steps. The five lithographic masking steps delineate in order:

REFERENCES:
patent: 3387286 (1968-06-01), Dennard
patent: 3653978 (1972-04-01), Robinson et al.
patent: 3696276 (1972-10-01), Boland
patent: 3775191 (1973-11-01), McQuhae
patent: 3811076 (1974-05-01), Smith
patent: 3865652 (1975-02-01), Agusta et al.
patent: 3886003 (1975-05-01), Takagi et al.
patent: 3897282 (1975-07-01), White
patent: 3936862 (1976-02-01), Moyle
patent: 3958323 (1976-05-01), De La Moneda
patent: 4033026 (1977-07-01), Pashley
Rideout, V. L., "Masking for One-Device Cell . . . Polysilicon Contacts", I.B.M. Tech. Discl. Bull., vol. 17, No. 9, Feb. 1975, pp, 2802-2804.
Bassous, E., "Fabricating Submicrometer Silicon Devices".
Ibid, vol. 15, No. 6, Nov. 1972, pp. 1823-1825.

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