Fabrication of insulated gate gallium arsenide FET with self-ali

Details Fabrication of insulated gate gallium arsenide FET with self-ali Fabrication of insulated gate gallium arsenide FET with self-ali

1986-04-07

1987-09-01

Hearn, Brian E.

Fishing, trapping, and vermin destroying

156643, 357 232, 357 233, 357 22, H01L 2100

Patent

active

046898697

ABSTRACT:
Disclosed is a process for forming a high-speed, self-aligned GaAs-gate field effect transistor with submicron channel length. Starting with a semi-insulating GaAs substrate having a thin gate insulator layer of undoped AlGaAs and a comparatively thick highly doped GaAs layer, a metal contacting the doped GaAs layer is controllably formed by sidewall image transfer and planarization etchback technique. The thickness and width of the metal strip are in the low submicron range. Using the metal strip as a mask, the doped GaAs is patterned into a GaAs gate for the FET having the characteristics of submicron width (i.e., the dimension of the gate measured along the source-drain), substantially vertical walls and contacted on the top thereof in a self-aligned relationship by the metal strip. Next, a submicron wide insulator sidewall is formed on the vertical walls of the gate. By ion implanation across the AlGaAs layer using the gate structure and a patterned photoresist as a mask, source and drain are formed in the substrate in self-aligned relation with the gate. Contact metallization is formed to electrically contact the source, drain and the gate.

REFERENCES:
patent: 4093503 (1978-06-01), Harris et al.
patent: 4354896 (1982-10-01), Hunter et al.
patent: 4358340 (1982-11-01), Fu
patent: 4419809 (1983-12-01), Riseman et al.
patent: 4430791 (1984-02-01), Dockerty
patent: 4432132 (1984-02-01), Kinsbron et al.
patent: 4445267 (1984-05-01), De La Moneda et al.
patent: 4587709 (1986-05-01), Fowler et al.
patent: 4645563 (1987-02-01), Terada
patent: 4648937 (1987-03-01), Ogura et al.
"Submicron-Gate Self-Aligned Gallium Arsenide FET Fabrication," (anon.), IBM Technical Disclosure Bulletin, vol. 22, No. 6, Nov. 1985, pp. 2687-2690.
Johnson et al., "Method of Making Submicron Dimensions in Structures Using Sidewall Image Transfer Techniques," IBM Technical Disclosure Bulletin, vol. 26, No. 9, Feb. 1984, pp. 4587-4589.
Jackson et al., "A Novel Submicron Fabrication Technique," IEDM, 1979, Conference Volume, pp. 58-61.
Hunter et al., "A New Edge-Defined Approach for Submicrometer MOSFET Fabrication," IEEE Electron Device Letters, vol. EDL-2, No. 1, Jan. 1981, pp. 4-6.
Ipri et al., "Submicrometer Polysilicon Gate CMOS/SOS Technology," IEEE Transactions on Electron Devices, vol. ED-27, No. 7, Jul. 1980, pp. 1275-1279.
Japanese Journal of Applied Physics, vol. 19, No. 5, May 1980, pp. 1225-1227, "A New Field-Effect Transistor with Selectively Doped GaAs
-Al.sub.x Ga.sub.1-x As Heterojunctions", by T. Mimura et al.
IEEE Electron Device Letters, vol. EDL-5, No. 9, Sep. 1984, pp. 379-381, "A GaAs Gate Heterojunction FET", by P. M. Solomon et al.
Electronics Letters, vol. 20, pp. 462-463, (1984), "n+-GaAs/Undoped GaAlAs/Undoped GaAs Field-Effect Transistor", by K. Matsumoto et al.
Electronics Letters, vol. 21, No. 13, Jun. 20, 1985, pp. 580-581, "p-Channel GaAs SIS, (Semiconductor-Insulator-Semiconductor) FET", by K. Matsumoto et al.

Affiliated with

Also associated with

Rating

Fabrication of insulated gate gallium arsenide FET with self-ali does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fabrication of insulated gate gallium arsenide FET with self-ali, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fabrication of insulated gate gallium arsenide FET with self-ali will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1256373