Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
1999-08-24
2001-08-28
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S111000, C438S112000
Reexamination Certificate
active
06281043
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to hybrid semiconductor devices, e.g., two-phase bridge rectifiers, and particularly to improvements in the apparatus and methods disclosed in U.S. Pat. No. 5,484,097, issued Jan. 16, 1996 (“the patent” hereinafter).
The patent (the subject matter of which is incorporated herein by reference) discloses a process for fabricating batches of individual devices disposed in rows and columns on a lead frame workpiece. Because all the devices are identical, details of the fabrication of but one such device are described. The patent process uses three lead frames wherein (for each device being simultaneously fabricated) two pairs of semiconductor chips are mounted on respective pairs of bonding pads of two of the lead frames. The three lead frames are then disposed one on top of the other with upper surfaces of the two chips on the bottom lead frame contacting under surfaces of the bonding pads of the overlying (middle) lead frame. The upper surfaces of the two chips on the bonding pads of the middle frame contact under surfaces of respective bonding pads of the top lead frame. The result is two stacks of two-chip stacks (for each device) with each chip being bonded between a pair of bonding pads integral with either the bottom and middle lead frames or the middle and top lead frames. Considering only the semiconductor chips in each device, eight joints (typically soldered) must be formed per device.
In the resulting bridge rectifier devices made according to the patent, each device includes four terminals, with each terminal being connected to a circuit node to which one electrode of a respective pair of chips is connected. A claimed feature in the patent is that all four device terminals lie in a common plane where they first exit a molded plastic envelope of each finished device. An advantage of this is discussed hereinafter. To achieve this feature, all four terminals comprise leads from the middle lead frame and, to this end, a respective internal electrical connection is provided between each pair of bonding pads on the top and bottom lead frames and the middle frame. This is accomplished by the provision, on the top and bottom lead frames, of respectively downwardly and upwardly bent cantilevered lead extensions from the bonding pads of the two lead frames. When the three lead frames are assembled one on top of the other, the upwardly extending lead extension from the bottom lead frame contacts the under surface of one lead terminal of the middle frame while the downwardly extending lead extension from the top lead frame contacts the upper surface of another lead terminal of the middle frame. The two lead extensions are then bonded, as by soldering, to the respective middle frame terminals. The soldering of the lead extensions to the middle lead frame terminals requires two additional joints, thus bringing to ten the total number of joints required in each device made according to the patent. The greater the number of joints in each device to be formed, the greater is the likelihood of defective devices. One improvement provided by the present invention is the elimination of two of the ten joints in each device.
In the process according to the patent, after all the ten joints are made, links joining the bonding pads of the top and bottom lead frames to their respective lead frames are severed, and the top and bottom frames are peeled off the workpiece. The remaining workpiece thus comprises only the middle lead frame, the two pairs of chips for each device secured to either upper or lower surfaces of respective pairs of bonding pads of the middle lead frame, and respectively downwardly and upwardly extending leads interconnecting the upwardly and downwardly facing bonding pads of respective pairs of chips to respective terminal leads of the middle frame.
Thereafter, the components of each device are plastic encapsulated using a known molding process with the result being that only portions of the middle lead frame extend outwardly from each molded device envelope. While not described in the patent, an important aspect of the molding process (in accordance with known practice) is that the parts to be encapsulated are disposed within a mold cavity into which a plastic molding component is injected under high pressure. Portions of the device not encapsulated extend outwardly through openings through walls of the cavity. Because of the pressure employed, which tends to force the potting compound through the smallest openings through the mold cavity walls, the preferred practice is to ensure that only single leads, in contrast to a laminate of layered leads, exit through the mold walls. If layered leads are present, it is quite difficult to prevent escape of the potting component between the layers. Additionally, even with single lead extensions from the mold cavity, a preferred practice is the use of dam bars (described further hereinafter) for limiting escape of the potting compound through the mold wall openings. The lead frame interconnecting arrangement disclosed in the patent, resulting in portions only of the middle frame exiting the mold cavity, is particularly compatible with known molding processes.
An attendant requirement in the patent, for performance of the above-described single frame encapsulation process, is that two of the lead frames be separated from the workpiece prior to encapsulation. This is accomplished, as described, by severing the links joining the bonding pads of the top and bottom lead frames to their respective lead frames after the chips are bonded in place. Such link severing, however, presents several problems. One is that, because the links are severed prior to device encapsulation, damage to the unencapsulated, hence unprotected chips, can occur. Other problems relate to the nature of the cutting operation (e.g., cutting through the links of the top and bottom frames while not damaging the middle frame) as well as to the fact that two separate frame cutting procedures are required; one before and one after device encapsulation.
Another improvement provided by the present invention is the elimination of the top and bottom link severing process.
SUMMARY OF THE INVENTION
Similarly as in the patent, three lead frames are used including pairs of interconnected bonding pads on each of the top and bottom lead frames. Each bonding pad pair of the top and bottom lead frames includes an integral extension bent out of the plane of its respective lead frame to provide a flat lead portion lying in the plane of the middle lead frame but not connected to the middle lead frame. Rather, the bonding pad extensions serve as links of the bonding pads to their respective lead frames and, in the completed, encapsulated devices, the flat lead portions serve as respective device terminals. Bonding pad links other than the bonding pad extensions are not used, hence no pre-encapsulation link cutting process is required. Also, because the bonding pad bent extensions are not connected to terminal lead portions of the middle frame, but serve themselves as device terminals, two of the ten solder joints required according to the patent are eliminated.
During the encapsulation process, all three lead frames are present but, at the mold cavity forming wall, only single leads, all lying in a common plane, pass through the mold wall. Additionally, the two bent extensions from the top and bottom lead frames cooperate to form, as hereinafter described, a planar dam bar.
REFERENCES:
patent: 5484097 (1996-01-01), Heuvel
patent: 5506174 (1996-04-01), Vandenheuval et al.
patent: 5508565 (1996-04-01), Hatakeyama et al.
patent: 5614759 (1997-03-01), Vandenheuvel et al.
patent: 5763829 (1998-06-01), Tomita et al.
patent: 5796162 (1998-08-01), Huang
patent: 0 228 869 (1987-07-01), None
Tummala, R et al., Microelectronics Packaging Handbook, Subsystem Packaging, Chapman & Hall, pp. 72-74, 1997.
Guillot Marie
McAuliffe Owen
O'Brien Tadhgh
O'Donoghue Finbarr
General Semiconductor Inc.
Jones Josetta I.
Mayer Fortkort & Williams, P.C.
Niebling John F.
Williams Karin L.
LandOfFree
Fabrication of hybrid semiconductor devices does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fabrication of hybrid semiconductor devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fabrication of hybrid semiconductor devices will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2466181