Fabrication of high power semiconductor devices with respective

Details Fabrication of high power semiconductor devices with respective Fabrication of high power semiconductor devices with respective

1997-12-18

2000-04-11

Utech, Benjamin

Semiconductor device manufacturing: process

Semiconductor substrate dicing

438171, 257 6, 257625, H01L 21265

Patent

active

060487771

ABSTRACT:
A low cost highly integrated method of fabricating a heat sink on the backside of a power semiconductor device maintains device performance, improves thermal transfer, and enables reliable planar connections without having to dice the wafer or package the discrete device-heat sink assembly. An etch stop layer is formed between the wafer and the frontside power devices to protect them during backside processing and to reduce the contact resistance between the device and its heat sink. The heat sinks are formed by thinning, patterning and then plating the wafer in such a manner that the devices can be released without dicing. The heat sinks are preferably oversized so that a vacuum tool can grasp the heat sink from above without damaging the device and then compression bond the heat sink onto a planar microstrip circuit assembly, which is designed and packaged to facilitate easy replacement of failed devices.

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K. Okaniwa et al., "A Novel FET Structure of Buried Plated Heat Sink for Superior High Performance GaAs MMICs", IEEE GaAs IC Symposium, 1990, pp. 233-236.
J.S. Kofol et al., "A Backside Via Process for Thermal Resistance Improvement Demonstrated Using GaAs HBTs", IEEE GaAs IC Symposium, 1992, pp. 267-270.

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