Fishing – trapping – and vermin destroying
Patent
1993-04-27
1994-05-03
Maples, John S.
Fishing, trapping, and vermin destroying
437230, 427 98, H01L 21441
Patent
active
053087968
ABSTRACT:
It has been found that selective metallization in integrated circuits is expeditiously achieved through a copper plating procedure. In this process, palladium silicide is used as a catalytic surface and an electroless plating bath is employed to introduce copper plating only in regions where the silicide is present. Use of this procedure yields superior filling of vias and windows with excellent conductivity.
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A. K. Datta, et al., "Characteristics of Metal-Semiconductor Contacts Fabricated by the Electroless Deposition Method," Solid State Electronics, 23(8), pp. 905-907 (Aug. 1980), Oxford, England.
Madokoro Shoji, "Manufacture of Semiconductor Integrated Circuit Device," Patent Abstracts of Japan, vol. 012217, Publ. No. JP63012155, (Jan. 19, 1988).
C. Y. Mak, et al., "Selective electroless copper metallization with palladium silicide on silicon substrates," Applied Physics Letters, 59(26), pp. 3449-3451 (Dec. 23, 1991).
Feldman Leonard C.
Higashi Gregg S.
Mak Cecilia Y.
Miller Barry
AT&T Bell Laboratories
Botos Richard J.
Maples John S.
Schneider Bruce S.
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