Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having air-gap dielectric
Reexamination Certificate
2003-12-15
2004-09-14
Smith, Metthew (Department: 2825)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having air-gap dielectric
C438S222000, C257S374000
Reexamination Certificate
active
06790745
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates a method for manufacturing semiconductor devices and more particular to a method for manufacturing smiconductor devices having isolated regions of silicon in a substrate.
Dielectrically isolation or “D.I.” Technology may be used to fabricate a variety of circuits with characteristics that cannot be obtained when using pn-junctions for isolation. Circuits that withstand high voltage, circuits that are resistant to high doses of radiation, and circuits that include radiation sensors such as photodiodes that are connected in series are examples. Unfortunately, the manufacturing techniques used to obtain dielectrically isolated regions are relatively expensive, so this technology has not been a cost effective option for many applications.
SUMMARY OF INVENTION
A new technique for obtaining dielectrically isolated regions of silicon in a substrate is disclosed. This technique differs from, and is less expensive than conventional approaches. This technique is used to form a layer of silicon dioxide below the isolated regions of silicon having a thickness that is selected from a relatively wide range. In a similar fashion, the thickness of the single crystal silicon layer that is dielectrically isolated is selected from a wide range to match the application. One version of this technique is described and shown in
FIGS. 1 through 14
. These figures show the use of an ion implantation step, which permanently damages the silicon to obtain regions of silicon that are subsequently etched away in the fabrication sequence. Argon ions are used to obtain damaged regions in silicon without doping it. Boron or indium ions are used if p-type doping of the silicon is acceptable, and phosphorus arsenic, or antimony are used if n-type doping of the silicon is acceptable. Ions of other atoms may be used as long as these ions create a damaged layer in the silicon without causing any other problems. It may also be possible to use oxygen or nitrogen implants at doses below those required to form a layer of SiO
2
or Si
3
N
4
or to use conventional thermal predeposition steps to obtain a damaged layer.
One of two different techniques is used to form the layer of SiO
2
below the regions of single crystal silicon. The damaged silicon may be etched directly, using an etchant that preferentially etches the damaged silicon, or heavily doped n-type silicon may be converted to “porous” silicon using an anodization process. (This process is described in the article “Galvanic Cell Formation: A review of Approaches to Silicon Etching for Sensor Fabrication,” by J. J. Kelly, X. H. Xia, C.M.A. Ashruf and P. J. French,
IEEE Sensors Journal
, Vol. 1, No. 2 (2001) pp. 127-142, incorporated herein by reference.)
As shown in
FIGS. 1-14
, the region of damaged silicon is preferentially removed later in the process, leaving a horizontal opening that is subsequently filled with silicon dioxide using thermal oxidation. The silicon region above the etched horizontal layer is held in place by material present in the perimeter trench, which is firmly attached to the silicon on both its inside and its outside walls.
The use of trenches with different widths allows the perimeter trench or the trenches along one axis to be completely filled, while the internal trenches or the trenches along the other orthogonal axis are not filled by the layer material or combination of materials that is grown and/or deposited following trench formation. Other combinations of trenches having different widths allow two-dimensional arrays of isolated single crystal regions of silicon to be formed. The only requirements are that the silicon must be removed from beneath the islands, and the islands must be held in place along at least one sidewall after the damaged silicon below the island is removed.
The use of the ion implantation step in
FIG. 2
to produce damaged silicon may be replaced by performing a conventional thermal predeposition or ion implantation to produce a heavily doped region if an etchant with a sufficiently high selectivity ratio for heavily doped silicon is used. The first three steps of this second version of this technique differ from those shown in
FIGS. 1-3
. These steps are shown in
FIGS. 15-17
. Following step
4
in
FIG. 4
, steps
5
through
13
of the first embodiment are completed, resulting in essentially the same structure shown in cross section FIG.
13
and from the top in FIG.
14
.
Alternately, the formation of the porous silicon as is taught in the incorporated reference may be used to remove a heavily doped n-type region that has been formed below the regions of single crystal silicon that are to be isolated. After the porous silicon is formed, the wafer is oxidized using an atmosphere containing water vapor, forming silicon dioxide. This silicon dioxide layer is next remove using an etchant containing HF. Finally, the wafer is oxidized, forming a layer of silicon dioxide on each silicon surface thick enough to fill the regions below and around each pillar of silicon.
The resulting semiconductor structure may be used in many application requiring isolated regions. In power ICs the power transistor may be placed on the isolated region and the control logic on non-isolated regions or visa versa. Similarly, in high frequency circuits the high frequency portion may be fabricated on the isolated pillars. The same techniques also apply to high-speed digital circuits. Finally the isolated islands may be use as charge storage elements.
FIGS. 6 and 14
show examples of the shapes of the dielectrically isolated regions that may be obtained. It is also possible to obtain square or rectangular areas of silicon that are dielectrically isolated having only perimeter trenches.
A number of other variations on this technique also exist. These variations include:
1. The formation of a dielectrically isolated layer of silicon without growing an epitaxial layer: The implant energy, implant dose, the atoms species used, and the details of any anneal determine the depth at which the damaged layer occurs. By using a high energy implanter or a relatively low mass ion, a thicker layer of silicon above the layer of silicon dioxide may be obtained. For some applications, this layer may be both thick enough and deep enough that no epitaxial deposition step is needed.
2. A wafer with a layer of silicon dioxide below the wafer surface that has been formed by ion implantation may be used as a starting point for this process. The thickness of the oxide layer may be increased to a value that is much greater than the one that can be obtained by the ion implantation of oxygen alone. The process steps of the first embodiment would be performed, but the ion implantation step would implant oxygen, forming a layer of silicon dioxide, before the rest of the steps in the first embodiment are performed. Variations of the specific steps may also be used without departing from the intention of this disclosure.
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Kelly, et al., Galvanic Cell Formation: A Review of Approaches to Silicon Etching for Sensor Fabrication, Aug. 2001, IEEE Sensors Journal, vol. 1, No. 2, p. 127-142.
Lee, The Fabrication of Thin, Freestanding, Single-Crystal, Semiconductor Membranes, Aug. 1990, J. Electochem. soc., vol. 137, No. 8,p. 2556-2574.
JBCR Innovations
Lee Calvin
Robinson Richard K.
Smith Metthew
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