Fabrication of dielectrically isolated fine line semiconductor t

Details Fabrication of dielectrically isolated fine line semiconductor t Fabrication of dielectrically isolated fine line semiconductor t

1985-12-05

1987-06-09

Powell, William A.

Electrical resistors

Strain gauge type

Fluid- or gas pressure-actuated

29 2535, 29610SG, 73721, 73727, 73DIG4, 148 15, 148187, 156630, 156631, 156633, 156644, 156653, 156657, 1566591, 156662, 338 42, 357 26, H01L 21306, B44C 122, G01B 716, H01C 1700

Patent

active

046723544

ABSTRACT:
There is disclosed apparatus and methods of fabricating a piezoresistive semiconductor structure for use in a transducer. According to one method, a layer of silicon dioxide is grown over the surface of a first semiconductor wafer which is designated as a carrier wafer. A layer of glas is then formed on the top surface of the carrier wafer over said layer of silicon dioxide. A second wafer has diffused therein a high conductivity semiconductor layer which is diffused on a top surface of a sacrificial semiconductor wafer. The first and second wafers are then bonded together by means of an electrostatic bond with the high conductivity layer of the sacrificial wafer facing the glass layer of the first wafer. After securing the wafers together, one may etch away the remaining portion of the sacrificial wafer to provide a high conductivity resistive layer which is secured to the glass layer of the first wafer and is patterned to form a resistive network using standard photolithographic making. In another embodiment, the sacrificial wafer is processed by means of a high conductivity diffusion procedure whereby a resistive line pattern is formed in the second wafer. After diffusion, the second wafer is etched so that the high conductivity pattern projects from the top surface. This top surface consisting of the projected high conductivity resistive pattern is then bonded to the glass layer of the second wafer. After bonding the two wafers together, the unwanted N-type regions of the sacrificial wafer are etched away using a conductivity selective etch to form the resistive pattern.

REFERENCES:
patent: 3819431 (1974-06-01), Kurtz et al.
patent: 3951707 (1976-04-01), Kurtz et al.
patent: 4016644 (1977-04-01), Kurtz et al.
patent: 4204185 (1980-05-01), Kurtz et al.
patent: 4481497 (1984-11-01), Kurtz et al.
patent: 4523964 (1985-06-01), Wilner et al.

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