Fabrication of devices having laterally isolated semiconductor r

Details Fabrication of devices having laterally isolated semiconductor r Fabrication of devices having laterally isolated semiconductor r

1989-03-23

1991-07-02

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 70, 437 72, H01L 21205, H01L 21285, H01L 21308

Patent

active

050285599

ABSTRACT:
A method of fabrication of a device having laterally isolated semiconductor regions. In a preferred embodiment, laterally isolated polysilicon features are created with vertical, nitride-sealed sidewalls. The nitride-sealed sidewalls formed using sidewall spacer technology eliminate oxide encroachment while further preventing the loss of dopant laterally during thermal processing. The final structure comprises polysilicon features flanked by either oxide isolation or additional polysilicon features and is planar without requiring a planarization etchback. The process is applicable to polysilicon electrodes over active areas as well as polysilicon resistors over isolation oxide.

REFERENCES:
Kure et al., "VLSI Device Fabrication Using a Unique, Highly-Selective Si.sub.3 N.sub.4 Dry Etching", International Electron Devices Meeting, Washington, D.C., Dec. 1983.

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