Fabrication of deep submicron structures and quantum wire transi

Details Fabrication of deep submicron structures and quantum wire transi Fabrication of deep submicron structures and quantum wire transi

1997-09-29

2000-05-16

Chaudhuri, Olik

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438946, 438947, H01L 2176

Patent

active

060636882

ABSTRACT:
The invention relates to a method of forming reduced feature size spacers. The method includes providing a semiconductor substrate having an area region; patterning a first spacer over a portion of the area region of the substrate, the first spacer having a first thickness and opposing side portions; patterning a pair of second spacers, each second spacer adjacent to a side portion of the first spacer, each second spacer having a second thickness in opposing side portions, wherein the second thickness is less than the first thickness; removing the first spacer; patterning a plurality of third spacers, each third spacer adjacent to one of the side portions of one of the second spacers, each one of the third spacers having a third thickness, wherein the third thickness is less than the second thickness; and removing the second spacers. The invention also relates to a field of effect transistor. The transistor includes a semiconductor substrate having a source region and a drain region; a gate area of the substrate surface; a channel region in the substrate having a cross-sectional area defined by a portion of the gate area, a channel length measured accross a portion of the channel region between the source region and the drain region; and a trench formed in a portion of the channel region, the trench having a trench length substantially equivalent to the channel length.

REFERENCES:
patent: 5482885 (1996-01-01), Lur et al.
S. Wolf, Silicon Processing for the VLSI Era, vol. 2, Lattice Press, pp. 45-58, 1990.

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