Fabrication of complementary bipolar transistors and CMOS device

Details Fabrication of complementary bipolar transistors and CMOS device Fabrication of complementary bipolar transistors and CMOS device

1980-02-25

1981-11-10

Dean, R.

Metal working

Method of mechanical manufacture

Assembling or joining

29571, 29578, 29591, 148174, 148187, 148189, 357 43, 357 44, 357 48, 357 71, H01L 2176, H01L 21441

Patent

active

042990246

ABSTRACT:
Specific impurity concentration regions are used for the simultaneous formation of CMOS devices and complementary bipolar transistors to produce high voltage, high performance bipolar transistors. The last diffusion step for shallow P.sup.+ and N.sup.+ emitter regions and contact regions is performed without a separate diffusion cycle. The formation of the gate oxide at a relatively low temperature is followed immediately by the formation of an undoped polysilicon gate layer. The polysilicon gate layer is doped to a reasonable resistance and also forms a first level interconnect. Phosphorous doped CVD silicon oxide is formed thereover and the top surface is treated with additional phosphorous to produce tapered contact apertures therethrough when etched. A layer of metal is applied and delineated to form contacts to the substrate regions and to form the second level of interconnects.

REFERENCES:
patent: 3576475 (1971-04-01), Kronlage
patent: 3609479 (1971-09-01), Lin et al.
patent: 3818583 (1974-06-01), Polata
patent: 3865649 (1975-02-01), Beasom
patent: 3892606 (1975-07-01), Chappelow et al.
patent: 3899373 (1975-08-01), Antipov
patent: 4075754 (1978-02-01), Cook
patent: 4120707 (1978-10-01), Beasom
patent: 4191603 (1980-03-01), Garbarino et al.

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