Fabrication of CMOS devices with reduced gate length

Details Fabrication of CMOS devices with reduced gate length Fabrication of CMOS devices with reduced gate length

1989-07-18

1991-01-22

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

H01L 21265

Patent

active

049870882

ABSTRACT:
A process for fabricating CMOS integrated devices includes forming an n-type deep well diffusion region in a surface of a p-type monocrystalline silicon substrate. Transistor devices having a p-type channel region are formed within the deep well diffusion regions, and transistor devices having an n-type channel region are formed external the deep well diffusion regions. The improvement of the present invention includes the step of performing an unmasked ion implantation of boron over the entire surface of the monocrystalline silicon substrate after having formed the deep well diffusion regions in order to effect simultaneously a partial compensation of a superficial doping level of the deep well diffusion region and an enrichment of a superficial doping level of the monocrystalline silicon substrate external the deep well diffusion region.

REFERENCES:
patent: 4459741 (1984-07-01), Schwabe et al.
patent: 4613885 (1986-09-01), Haken
patent: 4839301 (1989-06-01), Lee

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