Semiconductor device manufacturing: process – Making passive device – Planar capacitor
Patent
1998-01-05
2000-12-12
Monin, Jr., Donald L.
Semiconductor device manufacturing: process
Making passive device
Planar capacitor
438251, 438252, 438393, 438395, H01L 2120
Patent
active
061598194
ABSTRACT:
A method of fabricating of a capacitor with low voltage coefficient of capacitance is described. A silicon substrate with field oxide isolations is provided. A buried layer is formed by doping N-type impurities into the substrate as the bottom plate of the capacitor. A dielectric layer is formed by thermal oxidation for the capacitor, and then a polysilicon layer is formed by the low pressure chemical vapor deposition method. A thermal diffusion step is performed to dope phosphorus into the polysilicon layer. After formation of a polysilicide layer by the low pressure chemical vapor deposition method, arsenic ions are implanted into the polysilicon layer and the polysilicide layer. Finally the polysilicide layer and the polysilicon layer are partially etched in consequence, and the top plate of the capacitor is formed.
REFERENCES:
patent: 5338701 (1994-08-01), Hsu et al.
S.Wolf, Silicon Processing For The VLSI Era, vol. 1, pp. 181-182, 1986.
Fu Chun-Hsien
Lin Horn-Jaan
Tsai Ching-Huei
Monin, Jr. Donald L.
Pham Hoai
United Microelectronics Corp.
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