Fabrication of an integrated injection logic device with narrow

Details Fabrication of an integrated injection logic device with narrow Fabrication of an integrated injection logic device with narrow

1979-09-28

1981-01-06

Ozaki, G.

Metal treatment

Stock

Ferrous

148187, 148 33, 29571, 357 43, 357 46, 357 59, 357 92, 357 23, 357 91, H01L 2704, H01L 2122

Patent

active

042440017

ABSTRACT:
The basewidth of a lateral, bipolar transistor is markedly reduced by first forming a layer of polycrystalline silicon over an oxide coated substrate. By utilizing a process for doping the exposed edges of the patterned polysilicon layer, a narrower basewidth dimension is achieved than heretofore possible with photolithographic techniques.

REFERENCES:
patent: 3445734 (1969-05-01), Pecoraro et al.
patent: 3663869 (1972-05-01), Strull
patent: 3731164 (1973-05-01), Cheney
patent: 3738880 (1973-06-01), Laker
patent: 3846821 (1974-11-01), Nagata et al.
patent: 4069495 (1978-01-01), Masuoka
patent: 4124933 (1978-11-01), Nicholas
patent: 4183037 (1980-01-01), LeCan et al.

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