Fabrication of a nonvolatile memory array device

Details Fabrication of a nonvolatile memory array device Fabrication of a nonvolatile memory array device

1979-02-21

1981-07-21

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29591, 148 15, 148187, 357 41, 357 23, H01L 2126

Patent

active

042790697

ABSTRACT:
There is shown and described a memory array using MNOS/MOS transistors. The memory devices are nonvolatile, metal-nitride-oxide-semiconductor (MNOS) variable threshold voltage transistors and the metal-oxide semiconductor (MOS) input-output devices exhibit fixed threshold voltages. The MOS devices are fabricated first and the MNOS memory devices are fabricated thereafter. This memory gate last (MGL) arrangement eliminates the need for high temperature process steps after the formation of the MNOS device gate dielectric in the array devices. This operation results in an MNOS/MOS memory array which exhibits excellent ionizing radiation hardness characteristics as well as memory properties which are improved over present radiation hardened MNOS/MOS arrays.

REFERENCES:
patent: 3890632 (1975-06-01), Ham et al.
patent: 3974515 (1976-08-01), Ipri et al.
patent: 3978577 (1976-09-01), Bhattacharyya et al.
patent: 4002501 (1977-01-01), Tamura
patent: 4057824 (1977-11-01), Woods
patent: 4072974 (1978-02-01), Ipri
patent: 4075754 (1978-02-01), Cook
Saito et al., 2419 Jan. J. of Applied Physics, vol. 15, No. 7, 1976 Supp., pp. 185-190.
Cricchi et al., IEEE Trans. on Nuclear Sci., vol. NS-24, No. 6, Dec. 1977, pp. 2185-2189.

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