Optical waveguides – Integrated optical circuit
Reexamination Certificate
2001-12-11
2003-10-28
Healy, Brian (Department: 2874)
Optical waveguides
Integrated optical circuit
C385S131000, C385S132000, C438S029000, C438S031000
Reexamination Certificate
active
06640021
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the manufacture of integrated circuit devices. More particularly, this application relates to a process for integrating optoelectronic chips with chips fabricated using other technologies.
BACKGROUND OF THE INVENTION
The need for greater functionality and performance in semiconductor devices has resulted in the development of larger and more complex chips. In addition, it is often desirable to include several different functions on a single chip to obtain a “system on a chip,” which generally results in both an increased chip size and a more complicated manufacturing process. These factors both tend to depress manufacturing yield. It is estimated that many such complex chips, with areas greater than 400 mm
2
, will generally have very poor manufacturing yield (perhaps under 10%).
One method of maintaining acceptable yields is to manufacture smaller chips, and then to interconnect those chips on a single substrate or chip carrier. Besides improved manufacturing yield, another major advantage of this approach is that the individual chips may be of different sizes, perform different functions, or be fabricated by different or incompatible methods. A system constructed according to this approach is illustrated schematically in FIG.
1
. The substrate
1
has several chips
11
mounted thereon which have different sizes and functions. Chips
11
are interconnected either through conductors embedded in substrate
1
, or through a layer overlying the chips (not shown) containing wiring, so that a system on a chip is formed.
To effectively realize the advantages offered by the system-on-a-chip (SOC) concept, it is desirable for all of the different chip functions to be in very close proximity and have very precise alignment with respect to each other. For example, spacing
10
between chips
11
is preferably about 50 &mgr;m or less. The alignment and interconnection should also be performed with minimal added complexity in the overall process. In the case of an SOC, the interconnections should be made on top of the chips rather than in the chip carrier substrate.
Integrating optoelectronic chips with chips of other types poses a difficult challenge because very accurate chip placement is required. An optoelectronic chip having electrical input and light output must be placed so that it is both connected to the other chips in the system and at the same time coupled to a light-transmitting waveguide. For example, a light-emitting chip requiring a driver chip must be connected to the driver to receive signals therefrom. It is also desirable that the substrate have a built-in waveguide so that the light is efficiently transmitted.
There remains a need for a process for fabricating a device having a dense arrangement of chips and a high wiring density of chip-to-chip interconnections, which includes an optoelectronic chip and which can be practiced with high manufacturing yield.
SUMMARY OF THE INVENTION
The present invention addresses the above-described need by providing a process for integrating an optoelectronic chip and a driver chip on a substrate, and in which a waveguide is built into the substrate and the chips are joined to the substrate using a stud/via alignment technique.
In accordance with the invention, a waveguide structure is formed in the substrate; the waveguide structure includes a reflector and a channel for transmitting the light. A first layer is then formed on the substrate and overlying the waveguide structure. A stud is formed on the substrate in an opening in this layer. A second layer is formed on the chip, and a via is formed therein. The stud is then aligned to the via, thereby aligning the chip so that the light reaches the reflector through an opening in the first layer. The chip is then attached to the substrate.
In addition, electrical wiring is provided on the substrate, with electrical contact to the stud. Studs connected to different chips are therefore in contact, so that the chips are wired to each other. In particular, a driver chip may be mounted on the substrate along with the optoelectronic chip and connected thereto.
In one embodiment of the invention, a silicon substrate is used and the waveguide structure is formed therein. An angled surface is formed by etching a portion of the substrate; this angled surface is covered by a reflective layer. The waveguide is built in the etched portion; the waveguide has a first reflective layer, a light-transmitting layer and a second reflective layer. The waveguide is parallel to the substrate surface, and light falling incident onto the substrate normal to its surface is reflected by the angled reflector into the waveguide.
According to another embodiment of the invention, the waveguide structure is formed on a plate having a reflective layer and a light-transmitting layer (such as polyimide) deposited thereon. An opening is formed in the light-transmitting layer; the opening has an angled wall at an acute angle with respect to the surface of the plate, and a waveguide entry wall normal to the plate surface and opposite the angled wall. A second reflective layer is formed on a portion of the light-transmitting layer overlying the first reflective layer; the reflector is formed on the angled wall of the opening. The angled wall may be at an angle of 45° with respect to the surface of the plate, so that light normally incident on the plate enters the waveguide at normal incidence thereto.
According to a third embodiment of the invention, the waveguide structure is formed from a plate of light-transmitting material. A feature is formed in the plate which has a top surface and side surfaces; these will become the top and sides of the waveguide channel. A layer of cladding material is formed on these top and side surfaces. An adhesive layer is formed on the cladding layer, and a handling plate is attached to the adhesive layer. The bottom of the plate of light-transmitting material is then polished, to define the light transmitting channel. A second layer of cladding material is formed on the bottom surface of the channel, so that the channel and the layers of cladding material form a waveguide. A supporting plate is attached to the second layer of cladding material. The interface between the handling plate and the adhesive layer is then ablated using radiation transmitted through the handling plate, thereby detaching the handling plate.
The stud/via chip joining process permits placement of chips on the substrate with very high accuracy, and can accommodate chips of different sizes and technologies. By providing a process for building a light waveguide into the substrate, the present invention permits fabrication of a hybrid circuit having a driver chip and a light emitting chip.
REFERENCES:
patent: 4969712 (1990-11-01), Westwood et al.
patent: 5195154 (1993-03-01), Uchida
patent: 5249245 (1993-09-01), Lebby et al.
patent: 5319725 (1994-06-01), Buchmann et al.
patent: 5600741 (1997-02-01), Hauer et al.
patent: 5611008 (1997-03-01), Yap
patent: 5625734 (1997-04-01), Thomas et al.
patent: 5629534 (1997-05-01), Inuzuka et al.
patent: 5715338 (1998-02-01), Sjolinder et al.
patent: 5773897 (1998-06-01), Wen et al.
patent: 5972232 (1999-10-01), Lee et al.
patent: 6009218 (1999-12-01), Grand et al.
patent: 6088492 (2000-07-01), Kaneko et al.
patent: 6164836 (2000-12-01), Yamada et al.
patent: 6215585 (2001-04-01), Yoshimura et al.
patent: 6222951 (2001-04-01), Huang
patent: 6236774 (2001-05-01), Lackritz et al.
patent: 6243509 (2001-06-01), Chen
patent: 6438281 (2002-08-01), Tsukamoto et al.
patent: 6444560 (2002-09-01), Pogge et al.
patent: 2002/0061154 (2002-05-01), Tsukamoto et al.
U.S. Appl. No. 09/669,531, filed Sep. 26, 2000 entitled “Process for making fine pitch connections between devices and structure made by the process”. Pogge et al.
Pogge H. Bernhard
Prasad Chandrika
Yu Roy
Anderson Jay H.
Healy Brian
International Business Machines - Corporation
Wood Kevin S
LandOfFree
Fabrication of a hybrid integrated circuit device including... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fabrication of a hybrid integrated circuit device including..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fabrication of a hybrid integrated circuit device including... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3129677