Fabrication of a high density stacked gate EPROM split cell with

Details Fabrication of a high density stacked gate EPROM split cell with Fabrication of a high density stacked gate EPROM split cell with

1990-06-28

1992-02-25

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 49, 437195, 437979, H01L 2176

Patent

active

050913271

ABSTRACT:
A method for fabricating a split-gate EPROM cell utilizing stacked etch techniques is provided. In accordance with a preferred embodiment of the method, a layer of silicon dioxide is formed on a P- silicon substrate. A layer of polysilicon is formed on the silicon dioxide layer, followed by growth of an oxide
itride/oxide (ONO) layer. The ONO and polysilicon layers are etched to define floating gates. Next, an edge of each floating gate is utilized in a self-aligned implant of buried N+ bit lines. The floating gate extends only over a first portion of the channel defined between the adjacent buried bit lines. A differential oxide layer is grown on the substrate between adjacent floating gates in a low temperature steam oxidation step. That is, the oxide formed over the exposed portion of the buried N+ bit line is thicker than the oxide formed over the exposed portion of the channel. Following formation of the differential oxide layer, a second layer of polysilicon is formed and etched to define control lines extending perpendicular to the floating gates in the conventional split-gate EPROM cell structure. The control gates are utilized in a stacked etch to complete the split-gate cells. The etch is carried out such that the oxide overlying the N+ bit lines protect the surface of the substrate, avoiding bit line interruption, while the silicon dioxide overlying the exposed portion of the channel is overetched to form a trench into the channel that extends below the junction depth of the N+ region, thereby eliminating bit line to bit line reach-through.

REFERENCES:
patent: 4616402 (1986-10-01), Mori
patent: 4639893 (1987-01-01), Eitan
patent: 4698900 (1987-10-01), Esquivel
patent: 4795719 (1989-01-01), Eitan
patent: 4892840 (1990-01-01), Esquivel et al.
IEEE Cir. Conf., 2/77, Salsbury et al.
VLSI Cir. Conf., 1989, Ali et al.

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