Fabrication of a field effect transistor with an upside down...

Details Fabrication of a field effect transistor with an upside down... Fabrication of a field effect transistor with an upside down...

2001-02-12

2002-11-05

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Forming schottky junction

Compound semiconductor

C438S576000, C438S578000

Reexamination Certificate

active

06475890

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to fabrication of field effect transistors having scaled-down dimensions, and more particularly, to fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI (semiconductor on insulator) technology for minimizing short-channel effects and for maximizing drive current for the field effect transistor having scaled down dimensions of tens of nanometers.
BACKGROUND OF THE INVENTION
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to
FIG. 1
, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
100
which is fabricated within a semiconductor substrate
102
. The scaled down MOSFET
100
having submicron or nanometer dimensions includes a drain extension
104
and a source extension
106
formed within an active device area
126
of the semiconductor substrate
102
. The drain extension
104
and the source extension
106
are shallow junctions to minimize short-channel effects in the MOSFET
100
having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET
100
further includes a drain contact junction
108
with a drain silicide
110
for providing contact to the drain of the MOSFET
100
and includes a source contact junction
112
with a source silicide
114
for providing contact to the source of the MOSFET
100
. The drain contact junction
108
and the source contact junction
112
are fabricated as deeper junctions such that a relatively large size of the drain silicide
110
and the source silicide
114
respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET
100
.
The MOSFET
100
further includes a gate dielectric
116
and a gate electrode
118
which may be comprised of polysilicon. A gate silicide
120
is formed on the polysilicon gate electrode
118
for providing contact to the gate of the MOSFET
100
. The MOSFET
100
is electrically isolated from other integrated circuit devices within the semiconductor substrate
102
by shallow trench isolation structures
121
. The shallow trench isolation structures
121
define the active device area
126
, within the semiconductor substrate
102
, where the MOSFET
100
is fabricated therein.
The MOSFET
100
also includes a spacer
122
disposed on the sidewalls of the gate electrode
118
and the gate dielectric
116
. When the spacer
122
is comprised of silicon nitride (Si
3
N
4
), then a spacer liner oxide
124
is deposited as a buffer layer between the spacer
122
and the sidewalls of the gate electrode
118
and the gate dielectric
116
.
As the dimensions of the MOSFET
100
are scaled down to tens of nanometers, short-channel effects degrade the performance of the MOSFET
100
. Short-channel effects that result due to the short length of the channel between the drain extension
104
and the source extension
106
of the MOSFET
100
are known to one of ordinary skill in the art of integrated circuit fabrication. The electrical characteristics of the MOSFET
100
become difficult to control with bias on the gate electrode
118
with short-channel effects which may severely degrade the performance of the MOSFET.
Referring to
FIG. 2
, to enhance the control of electrical characteristics of a MOSFET
200
, a three-sided gate electrode
202
is formed to surround a pillar
204
of semiconductor material for the MOSFET
200
formed with SOI (semiconductor on insulator) technology.
FIG. 3
shows the cross sectional view of the three-sided gate electrode
202
across line A—A in FIG.
2
. The pillar
204
of semiconductor material is formed on a layer of buried insulating material
206
on a semiconductor substrate
208
in SOI (semiconductor on insulator) technology, as known to one of ordinary skill in the art of integrated circuit fabrication. Typically, the semiconductor substrate
208
and the pillar
204
are comprised of silicon, and the three-sided gate electrode
202
is comprised of polysilicon. In addition, the layer of buried insulating material
206
is comprised of silicon dioxide (SiO
2
).
A three-sided gate dielectric
210
is formed between the pillar
204
and the three sided gate electrode
202
. The three-sided gate dielectric
210
is comprised of one of silicon dioxide (SiO
2
), silicon nitride (Si3N4), or a dielectric material such as a metal oxide with a dielectric constant that is higher than the dielectric constant of silicon dioxide (SiO
2
).
Referring to
FIG. 2
, a drain and source dopant is implanted into the pillar
204
at a first side of the three-sided gate electrode
202
to form a drain
212
of the MOSFET
200
and at a second side of the three-sided gate electrode
202
to form a source
214
of the MOSFET
200
. A drain contact pad
216
is formed to provide connection to the drain
212
of the MOSFET
200
, and a source contact pad
218
is formed to provide connection to the source
214
of the MOSFET
200
.
Referring to
FIGS. 2 and 3
, the channel region of the MOSFET
200
is the gate length of the pillar
204
between the drain
212
and the source
214
and covered by the three-sided gate electrode
202
. Because charge accumulation within such a channel region is controlled by bias on the gate electrode
202
on three surfaces of the pillar (instead of just the one top surface of the semiconductor substrate
102
in the conventional MOSFET of FIG.
1
), electrical characteristics of the MOSFET
200
formed with SOI technology is more controllable to compensate for short-channel effects of the MOSFET
200
.
However, the effective drive current width of the MOSFET
200
may be limited.
FIG. 4
shows the cross-sectional view of the pillar
204
of
FIG. 3
with the pillar
204
and the gate dielectric
210
enlarged. The drain to source current of the MOSFET
200
is proportional to the effective drive current width of the MOSFET
200
. Referring to
FIG. 4
, the effective drive current width of the MOSFET
200
is the total perimeter distance of the gate dielectric
210
surrounding the pillar
204
including the height
220
of the pillar
204
for the first and second sides of the pillar
204
and the width
222
of the pillar
204
for the top surface of the pillar
204
. If “H” denotes the height
220
of the pillar
204
and “W” denotes the width
222
of the pillar
204
, then the effective drive current width “W
eff
” of the MOSFET
200
is as follows:
W
eff
=W
+2
xH
However, as the dimensions of the MOSFET
200
are scaled down for a smaller gate length of the pillar
204
from the drain contact
216
to the source contact
218
, etching processes have aspect ratio limitations such that the height
220
of the pillar
204
is limited, as known to one of ordinary skill in the art of integrated circuit fabrication. With a limited height
220
of the pillar
204
, the effective drive current width, W
eff
, and in turn the speed performance of the MOSFET
200
are disadvantageously limited.
Nevertheless, fabrication of the MOSFET
200
in SOI (semiconductor on insulator) technology with formation of the three-dimensional pillar
204
having gate bias at a plurality of sides of the pillar
204
is desirable for minimizing undesired short-channel effects. Thus, a mechanism is desired for maximizing the effective drive current of a MOSFET formed with the three-dimensional pillar having gate bias at a plurality of sides of the pillar
204
in SOI (semiconductor on insulator) technology.
SUMMARY OF THE INVENTION
Accordingly, in a general aspect of the present invention, a

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