Fabrication methods for memory cells

Details Fabrication methods for memory cells Fabrication methods for memory cells

2004-04-29

2008-08-12

Malsawma, Lex (Department: 2892)

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

Using structure alterable to conductive state

C257S530000, C257SE21350, C365S105000

Reexamination Certificate

active

07410838

ABSTRACT:
A memory cell and a method of fabricating the same. A first conductive layer on a substrate is provided and a first type doped semiconductor layer is then formed on the first conductive layer. The first type doped semiconductor layer and the first conductive layer are patterned into a first line. A dielectric layer is formed on the substrate with an opening exposing the first line. A column comprising a second diode component, a buffer layer, and an anti-fuse layer is formed in the opening. A second line is formed connecting the column on the dielectric layer running generally perpendicularly to the first line.

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