Fabrication methods for integration CMOS and BJT devices

Details Fabrication methods for integration CMOS and BJT devices Fabrication methods for integration CMOS and BJT devices

2011-08-30

2011-08-30

Vinh, Lan (Department: 1713)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S706000, C438S724000, C438S756000

Reexamination Certificate

active

08008212

ABSTRACT:
Fabrication methods for integrating CMOS and BJT devices are presented. A semiconductor substrate having a first region and a second region are provided, wherein the first region includes a CMOS device, and the second region includes a BJT device. A dielectric layer is conformably deposited on the semiconductor substrate. Part of the dielectric layer is removed, thereby forming sidewall spacers on a gate structure of the CMOS device and remaining a thin dielectric layer on the BJT device. The remaining thin dielectric layer is completely removed, completing integration of the CMOS device and the BJT device.

REFERENCES:
patent: 5273915 (1993-12-01), Hwang et al.
patent: 2007/0099406 (2007-05-01), Higashi et al.
patent: 2008/0003745 (2008-01-01), Myung et al.
patent: 101635279 (2010-01-01), None

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