Fabrication method of semiconductor memory device with...

Details Fabrication method of semiconductor memory device with... Fabrication method of semiconductor memory device with...

1999-09-14

2001-11-06

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S262000, C438S270000, C438S434000, C257S408000

Reexamination Certificate

active

06313009

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a fabrication method thereof, and in particular, to an improved semiconductor memory device and a fabrication method thereof which is capable of achieving a lightly doped drain (LDD) construction and reducing a parasitic capacitance generated between an impurity area and a word line by forming a trench in a portion of a semiconductor substrate and forming an impurity area around the trench.
2. Description of the Prior Art
FIG. 1
is a plan view of a layout of a semiconductor memory device according to the conventional art, and
FIG. 2
is a longitudinal cross-sectional view of the semiconductor memory device in FIG.
1
. As shown in these drawings, a semiconductor substrate
1
is formed having a plurality of (N+) impurity areas (
2
s
,
2
d
) on the upper portion thereof
1
, and on the plurality of impurity areas (N+) (
2
s
,
2
d
), a gate oxide film
3
is formed. On the gate oxide film
3
, a plurality of polysilicon lines
4
are sequentially formed. The polysilicon lines
4
which serve as word lines are formed to cross the plurality of (N+) impurity areas (
2
s
,
2
d
). And, a polysilicide layer
5
is formed on the polysilicons
4
.
In the above-described semiconductor memory device according to the conventional art, since as many capacitors as the (N+) impurity areas (
2
s
,
2
d
) (which are parasitic capacitors) are formed between the (N+) impurity areas (
2
s
,
2
d
) and the polysilicon lines
4
formed on the semiconductor substrate
1
, the delay time of the word lines is disadvantageously increased due to the parasitic capacitors, and it is difficult to reduce the size of a cell due to a lateral diffusion of the (N+) impurity areas (
2
s
,
2
d
). Furthermore, since the (N+) impurity areas (
2
s
,
2
d
) serve as the source and drain of a transistor, a semiconductor memory device having the LDD construction is impossible to fabricate.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an improved semiconductor memory device and a fabrication method thereof which is capable of lessening the parasitic capacitance formed due to polysilicon and (N+) impurity areas.
It is another object of the present invention to provide an improved semiconductor memory device and a fabrication method thereof which is capable of fabricating a semiconductor memory device having an LDD construction.
It is still another object of the present invention to provide an improved semiconductor memory device and a fabrication method thereof which is capable of reducing the size of a memory cell of a semiconductor device by preventing a lateral diffusion of an impurity area on a semiconductor substrate.
To achieve the above object, there is provided an improved semiconductor memory device which includes a semiconductor substrate, a plurality of trenches formed in the semiconductor substrate, first impurity areas formed along the outer surfaces of each of the plurality of trenches, second impurity areas formed under a bottom surfaces of each first impurity area along the outer surfaces of the trenches, an insulating film filled in each trench, a gate insulating film formed at a regular interval on the substrate having the insulating film filled in the trench, and a gate electrode formed on the gate insulating film.
To achieve the above object, there is provided an improved fabrication method for a semiconductor memory device which includes the steps of forming a plurality of trenches in a semiconductor substrate, forming a first impurity area around each trench, forming a second impurity area beneath each first impurity area, filling the trenches with an insulating film, forming a gate insulating film at a regular interval on the substrate having the insulating film filled in the trenches, and forming a gate electrode on the gate insulating film.


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patent: 4571819 (1986-02-01), Rogers et al.
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patent: 5424231 (1995-06-01), Yang
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patent: 5567635 (1996-10-01), Acovic et al.
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