Fabrication method of semiconductor memory device containing CMO

Details Fabrication method of semiconductor memory device containing CMO Fabrication method of semiconductor memory device containing CMO

1996-12-24

1997-12-09

Niebling, John

Fishing, trapping, and vermin destroying

437 57, H01L 21265, H01L 218238

Patent

active

056960123

ABSTRACT:
A fabrication method for a semiconductor memory device which remarkably improves a short-channel characteristic, and increases a driving electric current of the device by differently forming the thickness of side wall spacers formed at the sides of polysilicon gates in nMOS and pMOS regions, includes forming a gate insulating film on a semiconductor substrate having first and second regions, forming first and second gate electrodes in the first and second regions, respectively, on the substrate, forming a first conductive low concentration impurity area at the sides of the first gate electrode, forming a second conductive low concentration impurity area at the sides of the second gate electrode, forming a first insulating film on the substrate and a second insulating film on the first insulating film, stripping the second insulating film in the first region, forming first sidewall spacers at the sides of the first gate electrode, forming a first conductive high concentration impurity area in the substrate at the sides of the first gate electrode, forming second sidewall spacers composed of the first and second insulating films at the sides of the second gate electrode in the second region, and forming a second conductive high concentration impurity area in the substrate at the sides of the second gate electrode.

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Kang et al, VLSI Symposium, "New Transistor Structure Optimization for 0.25.mu.m CMOS Technology", pp. 85-86 (1991), month unknown.

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