Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
2003-02-12
2004-09-28
Zarneke, David A. (Department: 2827)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S123000, C438S124000, C264S272140, C264S272170, C264S500000
Reexamination Certificate
active
06797542
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a technique for use in fabricating a semiconductor integrated circuit device, and, more particularly, to a technique which is effective when applied to resin molding in an assembly using a matrix frame.
Resin molding techniques are described, for example, in Japanese Unexamined Patent Publication Nos. 2000-68305, Hei 11(1999)-297731, and 2000-164615.
Unexamined Patent Publication No. 2000-68305 discloses a technique in which the interior of a cavity is pressure-reduced prior to injection of resin into the cavity then, the cavity is pressurized almost simultaneously with the entry of the resin into the cavity and, thereafter, is pressure-reduced.
Unexamined Patent Publication No. Hei 11(1999)-297731, discloses a technique in which resin is charged into a cavity while pressurizing the interior of the cavity through air vents.
Unexamined Patent Publication No. 2000-164615, discloses a technique in which an air bleeder is formed in a press and cut relief plane of a resin sealing die, and residual air in a cavity and gas issuing from the molten resin are discharged to the exterior through the air bleeder.
SUMMARY OF THE INVENTION
If resin molding is performed in an assembly using a matrix frame, the charging speed of sealing resin differs between a first row of cavities located close to the pots of a molding die and a second row of cavities more widely spaced therefrom, the cavities being arranged in a matrix form, thus giving rise to the problem that the quality of the resulting product is deteriorated. That is, since the distance of the second row of cavities from the pots is longer than that of the first row of cavities, the resin charging speed for the second row of cavities is lower than that for the first row of cavities, thus leading to the deterioration of the quality of the produced product.
It is an object of the present invention to provide a method of fabricating a semiconductor integrated circuit device, which method can attain stabilization of the product quality.
It is another object of the present invention to provide a method of fabricating a semiconductor integrated circuit device, which method provides for an improvement in the freedom in developing a resin material of a sealing resin.
It is a further object of the present invention to provide a method of fabricating a semiconductor integrated circuit device, which method provides an improvement in the freedom of assembling conditions.
It is a still further object of the present invention to provide a method of fabricating a semiconductor integrated circuit device, which method can attain a reduction in the manufacturing cost.
The above and other objects and novel features of the present invention will become apparent from the following description and the accompanying drawings.
As to typical examples of in the present invention, a brief description will be given below.
In accordance with the present invention, the interiors of cavities arranged in a matrix form are pressurized and charged with a sealing resin in such a manner that the resin is charged at the same speed for all of the cavities.
Other more specific examples of the present invention will be described below:
1. A method of fabricating a semiconductor integrated circuit device, comprises the steps of:
(a) providing a lead frame on which plural device forming regions are arranged in a matrix form, the device forming regions each having a chip mounting portion and plural leads;
(b) mounting semiconductor chips, respectively, onto the chip mounting portions of the lead frame;
(c) disposing the lead frame with the semiconductor chips mounted thereon on a mold surface of a molding die, which mold surface includes cavities, and thereafter closing the molding die;
(d) pressurizing the interiors of the matrix cavities at a pressure in the range from 1 to 10 kg/cm
2
and charging a sealing resin into the thus-pressurized cavities; and
(e) after the step (d), dividing the lead frame into individual device forming regions.
2. A method of fabricating a semiconductor integrated circuit device, comprises the steps of:
(a) providing a multi-chip substrate on which plural device forming regions are arranged in a matrix form, the device forming regions each having a chip mounting region and plural leads;
(b) mounting semiconductor chips, respectively, onto the chip mounting regions of the multi-chip substrate, the semiconductor chips each having a thickness of 220 &mgr;m or less;
(c) disposing the multi-chip substrate with the semiconductor chips mounted thereon on a mold surface of a molding die, which mold surface includes a single cavity, and thereafter closing the molding die, while allowing the single cavity to cover all of the plural device forming regions;
(d) pressurizing the interior of the cavity, and charging a sealing resin into the thus-pressurized cavity; and
(e) after the step (d), dividing the multi-chip substrate into individual device forming regions.
REFERENCES:
patent: 4126292 (1978-11-01), Saeki et al.
patent: 5071334 (1991-12-01), Obara
patent: 5624691 (1997-04-01), Bednarz et al.
patent: 2002/0115237 (2002-08-01), Williams
patent: 11-297731 (1999-10-01), None
patent: 11-297731 (1999-10-01), None
patent: 2000-68305 (2000-03-01), None
patent: 2000-68305 (2000-03-01), None
patent: 2000-164615 (2000-06-01), None
Imura Kenichi
Kuratomi Bunshi
Murakami Fumio
Namiki Katsushige
Shimizu Fukumi
Antonelli Terry Stout & Kraus LLP
Renesas Technology Corp.
Zarneke David A.
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