Fabrication method of semiconductor integrated circuit device

Details Fabrication method of semiconductor integrated circuit device Fabrication method of semiconductor integrated circuit device

2007-06-26

2007-06-26

Nuynh, Andy (Department: 2818)

Semiconductor device manufacturing: process

With measuring or testing

Packaging or treatment of packaged semiconductor

C438S014000, C438S017000, C324S754090, C324S758010

Reexamination Certificate

active

10968431

ABSTRACT:
Any damage inflicted on test pads, inter-layer insulating films, semiconductor elements or wiring at the time of electrical inspection of semiconductor integrated circuit devices is to be reduced. Reinforcements having a substantially equal linear expansion ratio (coefficient of thermal expansion) relative to a wafer to be inspected are formed over an upper face of a thin film probe, grooves are cut in the reinforcements above the probes, a first elastomer which is softer than a second elastomer is so arranged as to fill the grooves and overflow the grooves by a prescribed quantity, a glass epoxy substrate, which is a multi-layered wiring board, is fitted over the second elastomer, and pads provided over an upper face of the glass epoxy substrate and bonding pads which are part of wirings belonging to the thin film probe are electrically connected by wires.

REFERENCES:
patent: 7049837 (2006-05-01), Kasukabe et al.
patent: 2002/0008529 (2002-01-01), Wilson et al.
patent: 2004/0070413 (2004-04-01), Kasukabe et al.
patent: 7-283280 (1995-10-01), None
patent: 8-50146 (1996-02-01), None
patent: 10-239348 (1998-09-01), None
patent: 2002-71719 (2002-03-01), None
patent: 2002-71720 (2002-03-01), None
patent: 2002-90387 (2002-03-01), None
JP 2002090387 A, Wilson et al., English Abstract.

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