Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2006-12-05
2006-12-05
Schillinger, Laura M. (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S107000, C438S123000
Reexamination Certificate
active
07144755
ABSTRACT:
At the time of performing resin molding for a matrix frame in the fabrication of semiconductor integrated circuit devices, a predetermined amount of air is fed into each of first cavities in a first row and second cavities in a second row, the first and second cavities being formed in a matrix arrangement in a lower mold of a molding die, so as to pressurize the interiors of the cavities, and a sealing resin is charged into the cavities, while the pressure therein is regulated in such a manner that the charging speeds of the sealing resin become equal in all of the cavities, whereby it is possible to stabilize the quality of the product being obtained.
REFERENCES:
patent: 4126292 (1978-11-01), Saeki et al.
patent: 5071334 (1991-12-01), Obara
patent: 5624691 (1997-04-01), Bednarz et al.
patent: 6350631 (2002-02-01), Kobayashi et al.
patent: 6469370 (2002-10-01), Kawahara et al.
patent: 6716553 (2004-04-01), Fujita et al.
patent: 6797542 (2004-09-01), Kuratomi et al.
patent: 6975022 (2005-12-01), Sakamoto et al.
patent: 6995038 (2006-02-01), Egawa et al.
patent: 2002/0019072 (2002-02-01), Kobayashi et al.
patent: 2002/0115237 (2002-08-01), Williams
patent: 2003/0153130 (2003-08-01), Kuratomi et al.
patent: 2005/0019979 (2005-01-01), Kuratomi et al.
patent: 2005/0070047 (2005-03-01), Kuratomi et al.
patent: 2005/0133895 (2005-06-01), Ujiie et al.
patent: 05-50456 (1993-03-01), None
patent: 07-164473 (1995-06-01), None
patent: 11-297731 (1999-10-01), None
patent: 11297731 (1999-10-01), None
patent: 2000-12598 (2000-01-01), None
patent: 2000-68305 (2000-03-01), None
patent: 2000-164615 (2000-06-01), None
patent: 2000-243876 (2000-09-01), None
patent: 2001-332649 (2001-11-01), None
patent: WO 00/68305 (2000-11-01), None
Imura Kenichi
Kuratomi Bunshi
Murakami Fumio
Namiki Katsushige
Shimizu Fukumi
Antonelli, Terry Stout and Kraus, LLP.
Eastern Japan Semiconductor Technologies, Inc.
Renesas Technology Corp.
Schillinger Laura M.
LandOfFree
Fabrication method of semiconductor integrated circuit device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Fabrication method of semiconductor integrated circuit device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fabrication method of semiconductor integrated circuit device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3675389