Fabrication method of semiconductor integrated circuit device

Metal fusion bonding – Process – Plural joints

Reexamination Certificate

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C228S228000, C228S234100

Reexamination Certificate

active

07861912

ABSTRACT:
Productivity is to be improved in assembling a semiconductor integrated circuit device. A matrix substrate is provided and semiconductor chips are disposed on a first heating stage, then the matrix substrate is disposed above the semiconductor chips on the first heating stage, subsequently the semiconductor chips and the matrix substrate are bonded to each other temporarily by thermocompression bonding while heating the chips directly by the first heating stage, thereafter the temporarily bonded matrix substrate is disposed on a second heating stage adjacent to the first heating stage, and then on the second heating stage the semiconductor chips are thermocompression-bonded to the matrix substrate while being heated directly by the second heating stage.

REFERENCES:
patent: 3617682 (1971-11-01), Hall
patent: 3946931 (1976-03-01), Bahnck et al.
patent: 4603802 (1986-08-01), Kurtz et al.
patent: 4605833 (1986-08-01), Lindberg
patent: 4607779 (1986-08-01), Burns
patent: 4883214 (1989-11-01), Zimmer
patent: 5425491 (1995-06-01), Tanaka et al.
patent: 5439161 (1995-08-01), Kawatani et al.
patent: 5573170 (1996-11-01), Sasaki et al.
patent: 5984165 (1999-11-01), Inoue et al.
patent: 6126059 (2000-10-01), MacKay et al.
patent: 6142356 (2000-11-01), Yamazaki et al.
patent: 6264089 (2001-07-01), Hasegawa et al.
patent: 6478906 (2002-11-01), Azdasht et al.
patent: 6494359 (2002-12-01), Hasegawa
patent: 6518095 (2003-02-01), Akutsu
patent: 6621157 (2003-09-01), Herbst et al.
patent: 6798072 (2004-09-01), Kajiwara et al.
patent: 7014092 (2006-03-01), Narita et al.
patent: 7075036 (2006-07-01), Ogimoto et al.
patent: 7118939 (2006-10-01), Imai
patent: 7299965 (2007-11-01), Sato
patent: 2001/0005603 (2001-06-01), Kubota
patent: 2001/0045445 (2001-11-01), Caletka et al.
patent: 2002/0092610 (2002-07-01), Funaya et al.
patent: 2004/0217100 (2004-11-01), Ogimoto et al.
patent: 2005/0155706 (2005-07-01), Nishida et al.
patent: 2006/0076388 (2006-04-01), Sato
patent: 2006/0113356 (2006-06-01), Matsumura et al.
patent: 2006/0126002 (2006-06-01), Morishita et al.
patent: 2008/0035274 (2008-02-01), Kanisawa
patent: 2008/0236876 (2008-10-01), Kodama et al.
patent: 2008/0247704 (2008-10-01), Kodama et al.
patent: 2009/0230171 (2009-09-01), Matsumura et al.
patent: 1 030 349 (2000-08-01), None
patent: 03-215951 (1991-09-01), None
patent: 5-2177 (1993-01-01), None
patent: 11-121532 (1999-04-01), None
patent: 2000-100837 (2000-04-01), None
patent: 2002-534799 (2002-10-01), None
patent: 2004-096048 (2004-03-01), None
Chinese Official Action dated Sep. 21, 2007, for Application No. 200410058682.8.

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