Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-09-28
2004-02-24
Karlsen, Ernest (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S754090, C438S017000
Reexamination Certificate
active
06696849
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a technique for fabricating a semiconductor integrated circuit device and a testing apparatus therefor; and, more specifically, the invention relates to a technique that can be applied, for example, to a burn-in test and probe test of a semiconductor integrated circuit device, and effectively can be applied particularly to a burn-in test of a semiconductor device in the wafer condition, that is, to a so-called wafer level burn-in test.
The present invention relates to a test technique and a fabrication technique applicable to a semiconductor integrated circuit device. According to investigations carried out by the inventors of the present invention regarding burn-in test techniques, for example, the official gazette of the Japanese Laid-Open Patent Applications Nos. HEI 11(1999)-97494, 9(1997)-148389 and “NIKKEI MICRO-DEVICE”, January 2000, pages 148 to 153 have been found to be relevant.
The official gazette of Japanese Laid-Open Patent Application No. HEI 11(1999)-97494 discloses a technique used to equalize the pushing pressure during testing by dividing the pushing member in order to share the pushing load between a plurality of places on the plane on the opposite side of the wafer relative to the pushing member when a plurality of probes provided on a membrane are pushed toward the wafer using the pushing member in the burn-in test of the wafer.
The official gazette of Japanese Laid-Open Patent Application No. HEI 9(1997)-148389 discloses a technique that uses a beam that maintains it elasticity toward the upper and lower directions on a silicon substrate with a micro-machining technique and also employs a micro-contact pin at an end of this beam in the layout provided at a position opposed to the electrode of a wafer, with a conductive thin film process being executed at the end of such micro-contact pin.
The reference “Nikkei MICRO-DEVICE, January, 2000” describes a system using a TPS (Three Parts Structure) probe, consisting of three parts including a multilayer wiring board, a thin film sheet with a bump and an anisotropic conductive rubber member, and a system in which a multilayer wiring board and a probe terminal are provided, the probe terminal having a structure in which a copper post is provided through a resin sheet, so that when pressure is applied, this copper post is crushed, whereby an unequal height of electrodes is equalized.
SUMMARY OF THE INVENTION
The inventors of the present invention have considered the technique used in the burn-in test as explained above and have established following conclusions.
For example, available semiconductor integrated circuit device test techniques include a burn-in test for screening a chip that may change to a defective chip when subjected to temperature and voltage stresses under a higher temperature atmosphere, a function test to check whether a device operates as specified for a predetermined function, and a probe test for determining good
o-good products by executing a test to determine the DC operation characteristic and AC operation characteristic thereof.
In recent years, in the burn-in test of a semiconductor integrated circuit device, the wafer level burn-in technique used to conduct a burn-in test in the wafer condition has been based on the requirement for coverage of wafer delivery (discrimination of quality) and KGD (Known Good Die)(improvement of yield of MCP (Multi-Chip Package)) and for relief of a no-good product for burn-in, feed-back of test data of a no-good product for burn-in and reduction of total cost or the like.
In this wafer level burn-in process, it is essential to solve certain technical problems, such as provision of a pushing mechanism that is able to realize equal pressurizing of the entire surface of a wafer, the provision of a wafer heating and temperature control mechanism, the requirement for a probe of ten thousand or more pins for covering the entire surface of the wafer, the need for absorption of warp and wave of the wafer surface and unequal heights of the probe, the dependence on the thermal expansion coefficient under higher temperature conditions, the layout of many wires, the necessity for gathering of input signals, the requirement for probe alignment to the entire surface of the wafer, the disconnection of a defective chip and cut-off of an over-current, and a contact check for the entire surface of wafer.
In regard to the burn-in test, to solve such technical problems, there has been proposed, for example, a technique described in the “NIKKEI MICRO-DEVICE, January, 2000”. However, this technique is assumed to include various problems, in that a film forming apparatus to eliminate a defective chip is required in the system utilizing the TPS probe described in the above publication, the wafer level burn-in may be executed only in the last stage of a probe test and laser relief, the contact resistance of a thin film sheet with a bump may be increased easily depending on the number of times of contact, a partial repair is impossible in the integrated structure, and the operation life of anisotropic conductive rubber is rather short.
Moreover, in the system utilizing the technique including the multilayer wiring board and probe terminal described in “NIKKEI MICRO-DEVICE, January, 2000”, there is assumed to be a problem in that a resin sheet is used only for a gold pad and this sheet is thrown away after it is once used.
It is an object of the present invention to provide a method of fabricating a semiconductor integrated circuit device and a method of testing the same device for realizing reduction in cost by employing a divided contactor integrating system, for example, in the burn-in test and probe test, particularly in wafer level burn-in, thereby realizing uniform contact of the divided contactors on the entire surface of the wafer, thereby enabling individual repair for each divided contactor and reducing the manufacturing cost through improvement of the yield of divided contactors.
The above and the other objects and novel features of the present invention will become apparent from the following description and the accompanying drawings.
The typical aspects of the invention among those disclosed in this specification will be briefly explained below.
(1) A testing apparatus of a semiconductor integrated circuit device comprises the following structural elements:
(a) a plurality of test styluses used to conduct an electric test in contact with a plurality of terminals provided on the first main plane of a wafer on which a plurality of semiconductor integrated circuit devices are formed;
(b) a single layer or multiple layers of the first wiring layer connected to a plurality of the test styluses; and
(c) a plurality of wiring/stylus composite plates wherein a plurality of the test styluses are held in a manner such that each tip thereof is projected toward the first main plane side and the first wiring layer is included respectively in each plate.
(2) In the testing apparatus of the semiconductor integrated circuit device of item (1), each plate of a plurality of wiring/stylus composite plates allocates test styluses to measure a plurality of chip regions formed on the first main plane of the wafer.
(3) In the testing apparatus of the semiconductor integrated circuit device of item (2), a plurality of terminals of the first chip region in a plurality of chip regions formed on the first main plane of the wafer are allocated to measure in contact with both test styluses of the first and second wiring/stylus composite plates among a plurality of wiring/stylus composite plates.
(4) In the testing apparatus of the semiconductor integrated circuit device of item (3), the number of wiring/stylus composite plates is 4 or more.
(5) In the testing apparatus of the semiconductor integrated circuit device of item (3), the number of wiring/stylus composite plates is 9 or more.
(6) In the testing apparatus of the semiconductor integrated circuit device of item (5), the number of chip regions to be measured with each plate amon
Ban Naoto
Hasebe Akio
Kohno Ryuji
Motoyama Yasuhiro
Namba Masaaki
Antonelli Terry Stout & Kraus LLP
Karlsen Ernest
Renesas Technology Corporation
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