Fabrication method of semiconductor device containing n- and p-c

Details Fabrication method of semiconductor device containing n- and p-c Fabrication method of semiconductor device containing n- and p-c

1995-08-01

1996-11-05

Fourson, George

Fishing, trapping, and vermin destroying

437 34, 437 45, 437 56, 437 58, 437 29, H01L 2170

Patent

active

055717454

ABSTRACT:
A fabrication method of an MOS semiconductor device through a reduced number of necessary resist mask formation steps. A patterned resist film is formed on an active region and an isolation insulator film. The resist film has a window exposing the active region and its surrounding area. First dopant ions are selectively implanted into the substrate using the patterned resist film as a mask, forming a well region of a first conductivity type. The first dopant ions penetrate through the gate electrode and the gate insulator film into the active region and through the isolation insulator film into the surrounding area of the active region. Second dopant ions are selectively implanted into the well region using the same patterned resist film as a mask, forming a pair of source/drain regions of a second conductivity type. The second dopant ions penetrate through the gate electrode and the gate insulator film into the well region and do not penetrate through the isolation insulator film. A patterned conductor film is formed on an interlayer insulator film.

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