Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
1997-08-29
2004-12-14
Goudreau, George A. (Department: 1763)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S595000, C438S783000, C438S784000, C438S751000
Reexamination Certificate
active
06831015
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and abrasive liquid used therein. More particularly, the present invention relates to a fabrication method of a semiconductor device including the step of planarizing an insulation film, and abrasive liquid used therein.
2. Description of the Background Art
Reducing the size of interconnections and providing multilayers are now required to further increase the integration density of semiconductor integrated circuit devices. An interlayer insulation film is provided between each interconnection to obtain a multilayer structure of the interconnection. If the surface of this interlayer insulation film is not planar, a step-graded portion will be generated at the interconnection formed above the interlayer insulation film. This will cause defects such as disconnection.
Therefore, the surface of the interlayer insulation film (the surface of the device) must be made as flat as possible. The technique to planarize the surface of the device is called planarization. This planarization technique has become important in reducing the size and providing multilayers of the interconnection.
The following two methods are known as conventional planarization techniques. As the first method, planarization using an SOG (Spin On Glass) film is known. The technique of planarization using an SOG film will be described hereinafter.
An SOG film is known as the most commonly used interlayer insulation film in the planarization art. In recent years, development in the planarization technique taking advantage of fluidity of a material of the interlayer insulation film is particularly noticeable.
An “SOG film” is a generic term of a film mainly composed of a solution in which a silicon compound is dissolved in an organic solvent, and silicon dioxide formed from that solution. In forming an SOG film, first a solution having a silicon compound dissolved in an organic solvent is applied in droplets while the substrate is rotated. By this rotation, the solution coating is provided so as to alleviate the step-graded portion on the substrate corresponding to the interconnection. More specifically, the coating is formed thick at the concave portion and thin at the convex portion on the substrate. Thus, the solution coating results in a planarized surface.
Heat treatment is then applied to vaporize the organic solvent. Also, polymerization proceeds to result in a planarized SOG film at the surface.
An SOG film is typically classified into an inorganic SOG film that does not include any organic component in the silicon compound, as represented by the following general formula (1), and an organic SOG film including an organic component in a silicon compound, as represented by the following general formula (2).
[SiO
2
]
n
(1)
[R
x
SiO
Y
]
n
(2)
(n, X, Y: integer; R: alkyl group or aryl group
An inorganic SOG film has a disadvantage that it is more brittle than a silicon oxide film formed by CVD (Chemical Vapor Deposition) in addition to being highly hygroscopic. For example, a crack is easily generated during the heat treatment in an inorganic SOG film when thicker than 0.5 &mgr;m.
In contrast, although an organic SOG film is highly hygroscopic, the organic SOG film is suppressed in generation of a crack during heat treatment. Therefore, the organic SOG film can be formed to a thickness to approximately 0.5-1.0 &mgr;m. That is: The usage of an organic SOG film allows the formation of a thicker interlayer insulation film. Therefore, sufficient planarization can be achieved even for a great step-graded portion on a substrate.
The second method of planarization employs chemical mechanical polishing (referred to as CMP hereinafter).
The CMP method is a process including chemical action in addition to mechanical polishing. For example, after a thick insulation film such as of silicon oxide is formed on a substrate by plasma CVD and the like, the insulation film is polished down to a predetermined film thickness by CMP. In this CMP method, polishing is carried out while applying an abrasive with colloidal silica as the main component.
Planarization using an SOG film is advantageous over one using an insulation film deposited only by CVD in that favorable planarization is achieved. However, this planarization of the current level in which complete planarization cannot be achieved is not sufficient to meet the potential high standard for an interlayer insulation film as microfabrication proceeds and the scale of integration increases since an SOG film is formed from liquid. It is therefore difficult to completely correspond to the microfabrication and high integration of the devices.
Planarization according to CMP is advantageous over planarization using SOG film in that planarization of a higher level can be achieved. However, when only an insulation film (for example, a silicon oxide film) formed by CVD is used as an interlayer insulation film as in the conventional case, it is difficult to embed an insulation film in microminiaturized interconnection without any gap. A void may be generated. Even if the interconnections are filled with an insulation film without any gap, the capacitance between the interconnections will become greater since the insulation film formed by CVD has a high relative dielectric constant. This causes the problem that the operating speed of the LSI will be degraded due to RC delay.
An approach of achieving a favorable planarized surface of an appropriate level by planarization using an SOG film, and then polishing the planarized surface by CMP for further planarization is conventionally known.
However, this process of polishing an SOG film by CMP induces problems set forth in the following. The polishing rate of an SOG film by CMP is lower than that of the case where an insulation film formed by CVD is polished by CMP. Therefore, the throughput is reduced to increase the cost for fabrication. There is also a problem that a defect such as a scratch (generated during polishing) is easily generated at the surface of the SOG film.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a fabrication method of a semiconductor device that allows improvement in planarization and polishing rate of an insulation film.
Another object of the present invention is to provide a fabrication method of a semiconductor device that can effectively prevent a defect from being generated in an insulation film during polishing working thereof.
According to an aspect of the invention, a fabrication method of a semiconductor device includes the following steps. First, impurities are introduced into a first insulation film. Then, planarization is carried out by polishing the surface of the first insulation film in which impurities are introduced. By carrying out polishing after impurities are introduced into the first insulation film, the polishing rate of the first insulation film by CMP is improved substantially to a level equal to the polishing rate of a silicon oxide film formed by CVD. Accordingly, the polish workability can be improved. Since polishing of the first insulation film is promoted by introduction of impurities thereto, the problem of generation of a defect such as a scratch during polishing of the first insulation film can be prevented effectively.
According to another aspect of the present invention, a method of fabricating a semiconductor device includes the following steps. A first insulation film is formed on a substrate. Then, a second insulation film is formed on the first insulation film. Impurities are introduced to at least the surface of the first insulation film before or after formation of the second insulation film. Planarization is achieved by polishing at least the second insulation film. By introducing impurities to at least the surface of the first insulation film, the portion where impurities are introduced has a polishing rate by CMP as high as that of a silicon oxide film formed by CVD.
Inoue Yasunori
Okayama Yoshio
Goudreau George A.
Sanyo Electric Co,. Ltd.
Westerman Hattori Daniels & Adrian LLP
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