Fabrication method of self-aligned ferroelectric gate...

Details Fabrication method of self-aligned ferroelectric gate... Fabrication method of self-aligned ferroelectric gate...

2006-12-19

2006-12-19

Baumeister, B. William (Department: 2891)

Semiconductor device manufacturing: process

Having magnetic or ferroelectric component

C257S295000, C257S306000, C257S665000, C257SE21436, C257SE21663

Reexamination Certificate

active

07151001

ABSTRACT:
A fabrication method of a self-aligned ferroelectric gate transistor using a buffer layer of high etching selectivity is disclosed. A stacked structure is formed with a buffer layer with high etching selectivity inserted between a silicon substrate and a ferroelectric layer, and etching is performed on a portion where a source and a drain will be formed and then stopped at the buffer layer, thereby fabricating a self-aligned ferroelectric gate transistor without damage to the silicon thin film, and thus, an integration degree of a chip can be improved.

REFERENCES:
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patent: 6124620 (2000-09-01), Gardner et al.
patent: 6194752 (2001-02-01), Ogasahara et al.
patent: 6608339 (2003-08-01), Tarui et al.
patent: 11026704 (1999-01-01), None

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