Fabrication method of optical device having current blocking...

Details Fabrication method of optical device having current blocking... Fabrication method of optical device having current blocking...

2002-04-03

2003-11-25

Thomas, Tom (Department: 2811)

Semiconductor device manufacturing: process

Making device or circuit emissive of nonelectrical signal

Compound semiconductor

C438S040000, C438S041000, C438S044000, C257S094000, C257S096000, C372S045013, C372S046012

Reexamination Certificate

active

06653162

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an optical device; and, more particularly, to a current blocking layer structure of an optical device having a buried ridge structure (BRS) and a fabrication method thereof.
DESCRIPTION OF RELATED ART
Generally, optical devices used for an optical fiber communication, e.g., a high-performance semiconductor laser diode (LD) or a semiconductor optical amplifier (SOA), requires a low threshold current and high quantum efficiency, and for this, leakage current should be minimized.
To minimize the leakage current, semiconductor lasers using a planar buried heterostructure (PBH) and a buried ridge structure (BRS) are used. The optical source and the optical amplifier used in the optical fiber communication need to be high-powered, highly reliable and perform at a high speed. Therefore, it is necessary to optimize a current blocking layer used in these structures.
To form such a current blocking layer, three methods are used commonly.
The first method is what uses a P-N-P current blocking structure. It is based on a principle that when an electric current is supplied to an electrode, the current is blocked because other parts except an active layer is supplied with a reverse bias, while the active-layer receives a forward bias. This is a first conventional method to be described below.
Secondly, there is a method that grows a semi-insulation layer and uses it as a current blocking layer. As for the semi-insulation layer, iron (Fe) is usually doped and used. This is a second conventional method that will be also described later on.
The third conventional method is to implant hydrogen ions into the parts except the active layer and block a current.
<Conventional Method 1>
FIGS. 1A
to
1
E are cross-sectional views illustrating a first method for fabricating a conventional optical device of a planar buried heterostructure having a P-N-P current blocking layer.
First, as described in
FIG. 1A
, an active layer
102
of a heterostructure and a p-InP layer
103
are grown on an n-InP substrate
101
with a liquid phase epitaxy (LPE) or a metalorganic chemical vapor deposition (MOCVD), and an insulation layer mask
104
for a mesa-etching is formed on top of the p-InP layer
103
in a photolithography etching process.
Subsequently, as shown in
FIG. 1B
, the p-InP layer
103
, the active layer
102
and a part of the n-InP substrate
101
are etched by using the insulation layer mask
104
, but a mesa structure is formed through the processes of dry-etching and wet-etching.
Subsequently, as depicted in
FIG. 1C
, to confine the current and optical ray of the active layer
102
, a p-InP
105
and an n-InP
106
are grown again in the LPE or MOCVD method.
Subsequently, as illustrated in
FIG. 1D
, after removing the insulation layer mask
104
used for the mesa-etching, a p-InGaAs layer
108
for ohm(&OHgr;)-contacting with a p-InP clad layer
107
is grown again in the LPE or the MOCVD method.
Subsequently, as described in
FIG. 1E
, the region overlapped with the upper part of the active layer
102
is open by depositing an insulation layer
109
on the p-InGaAs layer
108
and performing a photolithography etching process, and a p-electrode
110
and an n-electrode
111
are formed to contact with the p-InGaAs layer
108
and the n-InP substrate
101
, respectively.
In the first conventional method described above, in case of a one-layer waveguide, the good static characteristics can be obtained by re-growing the P-N-P. However, in case that the waveguide is of complicated structure with two or more layers in the vertical direction for the integration of an optical device, it is not only hard to re-grow the P-N-P current blocking structure, but a problem of increasing leakage current is raised, even if the P-N-P is re-grown.
<Conventional Method 2>
FIGS. 2A
to
2
E are cross-sectional views describing a second method for fabricating a conventional optical device of a planar buried heterostructure having a semi-insulation current blocking layer.
First, as illustrated in
FIG. 2A
, an active layer
202
and a p-InP layer
203
are grown on an n-InP substrate
201
in a liquid phase epitaxy (LPE) or a metalorganic chemical vapor deposition (MOCVD) method, and an insulation layer mask
204
for the mesa-etching is formed on top of the p-InP layer
203
in a photolithography etching process.
Subsequently, as shown in
FIG. 2B
, the p-InP layer
203
, the active layer
202
and a part of the n-InP substrate
201
are etched by using the insulation layer mask
204
, but a mesa structure is formed through the processes of dry-etching and wet-etching.
Subsequently, as depicted in
FIG. 2C
, to confine the current and optical ray of the active layer
202
, a semi-insulation InP current blocking layer
205
is grown again in the LPE or MOCVD method.
Subsequently, as illustrated in
FIG. 2D
, after removing the insulation layer mask
204
used for the mesa-etching, a p-InGaAs layer
207
for ohm(&OHgr;)-contacting with a p-InP clad layer
206
is grown again in the LPE or the MOCVD method.
Subsequently, as described in
FIG. 2E
, the region overlapped with the upper part of the active layer
202
is open by depositing an insulation layer
208
on the p-InGaAs layer
207
and performing a photolithography etching process, and a p-electrode
209
and an n-electrode
210
are formed to contact with the p-InGaAs layer
207
and the n-InP substrate
201
, respectively.
The second conventional method described above has advantages that it solves the problem of increasing parasitic capacitance, which is caused in the aforedescribed first conventional method, and improves the property of high-speed modulation, and that it simplifies the processes.
However, since the semi-insulation layer used as a current blocking layer works as a deep level center in which holes and electrons are combined, it is more likely to work as a path for leakage current than as a current blocking layer. Also, there is a problem that the performance of the active layer is degraded due to the diffusion of iron (Fe), which is used as a doping impurity for forming a semi-insulation layer.
<Conventional Method 3>
FIGS. 3A
to
3
E are cross-sectional views showing a third method for fabricating a conventional optical device of a buried ridge structure having a current blocking layer using a hydrogen ion implantation method.
First, as illustrated in
FIG. 3A
, an active layer
302
and a p-InP layer
303
are grown on an n-InP substrate
301
in a liquid phase epitaxy (LPE) or a metalorganic chemical vapor deposition (MOCVD) method, and an insulation layer mask
304
for the mesa-etching is formed on top of the p-InP layer
303
in a photolithography etching process.
Subsequently, as shown in
FIG. 3B
, the p-InP layer
303
, the active layer
302
and a part of the n-InP substrate
301
are etched by using the insulation layer mask
304
, but a mesa structure is formed through the processes of dry-etching and wet-etching.
Subsequently, as depicted in
FIG. 3C
, to confine the current and optical ray of the active layer
302
, the insulation layer mask
304
is removed and a p-InGaAs layer
306
is grown again to ohm-contact with a p-InP clad layer
305
in the LPE or MOCVD method.
Subsequently, as illustrated in
FIG. 3D
, to form a current blocking layer using hydrogen ion implantation, a hydrogen ion blocking mask
307
is formed overlapped with the active layer
302
in a photolithography etching process, and a current blocking layer
308
is formed by using the hydrogen ion implantation method.
Subsequently, as described in
FIG. 3E
, after removing the hydrogen ion blocking mask
307
, a region overlapped with the upper part of the active layer
302
is open by depositing an insulation layer
309
on the p-InGaAs layer
306
and performing a photolithography etching process, and a p-electrode
310
and an n-electrode
311
are formed to contact with the p-InGaAs layer
306
and the n-InP substrate
301
, respectively.
The third conventional method described

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