Fabrication method of field-effect transistor

Details Fabrication method of field-effect transistor Fabrication method of field-effect transistor

1995-03-30

1996-03-19

Nguyen, Tuan H.

Fishing, trapping, and vermin destroying

437 44, 437 39, 437133, 437176, 437912, 148DIG100, H01L 21338

Patent

active

055003818

ABSTRACT:
A fabrication method of a FET that enables to realize a shorter length between a source-side edge of a recess and an opposing edge of a gate electrode at a higher accuracy than the accuracy limit of the present lithography technique, i.e., about .+-.0.1 .mu.m. After channel, carrier-supply, and contact layers are epitaxially grown on a semiconductor substrate in this order, a patterned insulator layer is formed on the contact layer. Using the insulator layer as a mask, the contact layer is isotropically etched to form a symmetrical recess on the underlying carrier-supply layer. One of the ends of the contact layer facing the symmetrical recess is etched again to make it asymmetric. During the etching processes, the underlying carrier-supply layer is almost never etched due to large etch rate differences for the contact layer and the carrier-supply layer. A patterned conductor layer is formed on the patterned insulator layer to form the gate electrode in Schottky contact with the carrier-supply layer. After removing the insulator layer, and source and drain electrodes are formed on the contact layer. An etch-stop layer is additionally formed between the carrier-supply layer and the contact layer.

REFERENCES:
patent: 4525919 (1985-07-01), Fabian
patent: 5006478 (1991-04-01), Kobayashi et al.
patent: 5110751 (1992-05-01), Nakagawa
patent: 5112763 (1992-05-01), Taylor et al.
patent: 5231040 (1993-07-01), Shimura

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