Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2011-03-15
2011-03-15
Le, Thao X (Department: 2893)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S613000, C257SE23038
Reexamination Certificate
active
07906377
ABSTRACT:
A fabrication method of a circuit board is provided. A substrate, a top pad, a base pad electrically connecting the top pad, and a top and a base solder resist layers are provided. The top and the base pads are disposed on two opposite surfaces of the substrate, respectively. The top solder resist layer having a first opening partially exposing the top pad and the base solder resist layer having a second opening partially exposing the base pad are disposed on the two surfaces, respectively. A conductive layer covering the base solder resist layer and the base pad is formed. A plating resist layer having a third opening is formed on the conductive layer. A current is applied to the conductive layer through the third opening for electroplating a pre-bump on the top pad. The plating resist layer and the conductive layer are then removed.
REFERENCES:
patent: 6872590 (2005-03-01), Lee et al.
patent: 2002/0190376 (2002-12-01), Sato
patent: 1620230 (2005-05-01), None
patent: 101252092 (2008-08-01), None
Chang Wen-Yuan
Chen Wei-Cheng
Hsu Yeh-Chi
J.C. Patents
Le Thao X
Trinh Hoa B
VIA Technologies Inc.
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